Hi! On Fri, Nov 13, 2020 at 04:04:30PM -0600, Pat Haugen wrote: > gcc/ > * config/rs6000/rs6000.c (struct processor_costs): New.
Will already commented on this; please consider his comments :-) > (rs6000_option_override_internal): Set Power10 costs. > (rs6000_issue_rate): Set Power10 issue rate. > * config/rs6000/power10.md: Rewrite for Power10. > +(define_automaton "power10dsp,power10issue,power10div") Write "dispatch" in full? It is only used here and in the du*_power10 definition. Or does it show up in debug dumps too much, or similar? > +(define_insn_reservation "power10-load-update" 4 > + (and (eq_attr "type" "load") > + (eq_attr "update" "yes") > + (eq_attr "cpu" "power10")) > + "DU_even_power10,LU_power10+SXU_power10") Maybe make a bypass (or however you can model this) for the updated register? That is only 2 cycles, right? > +(define_insn_reservation "power10-mul" 5 This makes the power10_costs entries somewhat questionable. > +(define_insn_reservation "power10-div" 12 And this (and the other division latencies). Please check Will's comments too, and (build) test on both BE and LE. With that, okay for trunk, and thank you! Segher
