On 11/19/20 8:35 PM, Maciej W. Rozycki wrote:
> It makes no sense for insn operand predicates, as long as they accept a
> register operand, to be more restrictive than the set of the associated
> constraints, because expand will choose the insn based on the relevant
> operand being a pseudo register then and reload keep it happily as a
> memory reference if a constraint permits it. So the restriction posed
> by such a predicate will be happily ignored, and moreover if a splitter
> is added, such as required for MODE_CC support, the new instructions
> will reject the original operands supplied, causing an ICE. An actual
> example will be given with a subsequent change.
>
> Remove such inconsistencies we have with the EXTV/EXTZV/INSV insns then,
> observing that a bitfield located in memory is byte-addressed by the
> respective machine instructions and therefore SImode may only be used
> with a register or an offsettable memory operand (i.e. not an indexed,
> pre-decremented, or post-incremented one), which has already been taken
> into account with the constraints currently used, except for `*insv_2'.
> The QI machine mode may be used for the bitfield location with any kind
> of memory operand, but we got the constraint wrong, although harmlessly
> in reality, with `*insv'. Fix that for consistency though.
>
> Also give the insns names, for easier reference here and elsewhere.
>
> gcc/
> * config/vax/vax.md (*insv_aligned, *extzv_aligned)
> (*extv_aligned, *extv_non_const, *extzv_non_const): Name insns.
> Fix location predicate.
> (*extzv): Name insn.
> (*insv): Likewise. Fix location constraint.
> (*insv_2): Likewise, and the predicate.
OK.
jeff
