On 11/19/20 8:35 PM, Maciej W. Rozycki wrote:
> Our `ffssi2_internal' pattern and the machine FFS instruction, which
> technically is a bitfield operation, match the `ctz' operation exactly,
> with the result produced for the bitfield source operand of zero equal
> to its width as specified with another machine instruction operand, not
> directly expressed in RTL and currently hardcoded in the assembly code
> produced.  In our terms this is the bit size of the machine mode used,
> and although it's SImode now let's be flexible for an upcoming change.
>
> The operation also sets the Z condition code according to the value of
> the source operand.
>
>       gcc/
>       * config/vax/builtins.md (ffssi2_internal): Rename insn to...
>       (ctzsi2): ... this.  Update the RTL operation.
>       (ffssi2): Update accordingly.
>       * gcc/config/vax/vax.c (vax_notice_update_cc): Handle CTZ.
>       * gcc/config/vax/vax.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro.
>
>       gcc/testsuite/
>       * gcc.target/vax/ctzsi.c: New test.
OK
jeff

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