Hi! On Thu, Sep 24, 2020 at 04:56:27PM -0400, Michael Meissner wrote: > On Thu, Sep 24, 2020 at 10:24:52AM +0200, Florian Weimer wrote: > > * Michael Meissner via Gcc-patches: > > > > > These patches are my latest versions of the patches to add IEEE 128-bit > > > min, > > > max, and conditional move to GCC. They correspond to the earlier patches > > > #3 > > > and #4 (patches #1 and #2 have been installed). > > > > Is this about IEEE min or IEEE minimum? My understanding is that they > > are not the same (or that the behavior depends on the standard version, > > but I think min was replaced with minimum in the 2019 standard or > > something like that).
This is about the GCC internal RTX code "smin", which returns an undefined result if either operand is a NAN, or both are zeros (of different sign). > The ISA 3.0 added 2 min/max variants to add to the original variant in power7 > (ISA 2.6). 2.06, fwiw. > xsmaxdp Maximum value > xsmaxcdp Maximum value with "C" semantics > xsmaxjdp Maximum value with "Java" semantics xsmaxdp implements IEEE behaviour fine. xsmaxcdp is simply the C expression (x > y ? x : y) (or something like that), and xsmaxjdp is something like that for Java. > Due to the NaN rules, unless you use -ffast-math, the compiler won't generate > these by default. Simply because the RTL would be undefined! > In ISA 3.1 (power10) the decision was made to only provide the "C" form on > maximum and minimum. ... for quad precision. Segher
