On Thu, 3 Sep 2020, Alexandre Oliva wrote:
> On Sep 3, 2020, Segher Boessenkool <seg...@kernel.crashing.org> wrote:
> > For instructions that inherently set a condition code register, the
> > @code{compare} operator is always written as the first RTL expression of
> > the @code{parallel} instruction pattern.
>
> Interesting. I'm pretty sure I read email recently that suggested it
> was really up to the port, but I've caught up with GCC emails from years
> ago, so that might have been it. Or I just misremember. Whatever.
If you remember far enough back, you were right. :)
As I recall it, at one time, it was up to the port. Then, some
time after the x86 port was decc0rated, and cc0 judged evil (but
before the infrastructure changes to seriously support
decc0ration), it became important and there was a discussion on
canonicalizing the order. I remember arguing for the
flags-setting to be last in the parallel, consistent with the
clobber canonically being last and the "important" part of the
insn should be first, (possibly also having observed combine
ordering as you did) but that's not the way it turned out.
I have a faint memory about the order in the x86 patterns even
being used as an argument!
> Since there is a canonical order, maybe combine should attempt to follow
> that order.
> Anyway... Does this still seem worth pursuing?
Are you referring to your non-flags-clobbering or making combine
order flags-side-effect parallels canonically?
I don't have an opinion in the former, but IMHO, yes, getting
the combined order right seems worthwile. (No, I have no
targets that'd benefit from this.)
brgds, H-P
