Hi!
On Thu, Sep 03, 2020 at 04:31:35PM -0300, Alexandre Oliva wrote:
> Except when it doesn't ;-)
Heh. PRs welcome :-)
> Under:
>
> /* If the actions of the earlier insns must be kept
> in addition to substituting them into the latest one,
> we must make a new PARALLEL for the latest insn
> to hold additional the SETs. */
>
> it turns the RMW add pattern into a PARALLEL and adds to it i0's
> flags-setter, that had been split out of i2. The PARALLEL
> has the flag-setter as the second in the parallel, as you can see below,
> and nothing (other than my patch) attempts to change that order.
Please open a PR? (But see below first.)
> > What does that RTL look like exactly?
>
> Trying 5, 7 -> 15:
> 5: r91:SI=zero_extend([`i'])
> 7: {flags:CCC=cmp(r91:SI#0+0x1,r91:SI#0);r92:QI=r91:SI#0+0x1;}
> REG_DEAD r91:SI
> 15: [`i']=r92:QI
> REG_DEAD r92:QI
> Successfully matched this instruction:
> (parallel [
> (set (mem/c:QI (symbol_ref:DI ("i") [flags 0x2] <var_decl
> 0x7ffff7ff7b4
> 0 i>) [0 i+0 S1 A8])
> (plus:QI (mem/c:QI (symbol_ref:DI ("i") [flags 0x2] <var_decl
> 0x7ff
> ff7ff7b40 i>) [0 i+0 S1 A8])
> (const_int 1 [0x1])))
> (set (reg:CCC 17 flags)
> (compare:CCC (plus:QI (mem/c:QI (symbol_ref:DI ("i") [flags 0x2]
> <var_decl 0x7ffff7ff7b40 i>) [0 i+0 S1 A8])
> (const_int 1 [0x1]))
> (mem/c:QI (symbol_ref:DI ("i") [flags 0x2] <var_decl
> 0x7ffff7ff7b40 i>) [0 i+0 S1 A8])))
> ])
This isn't the case with the canonical form (the compare is not a
compare against 0).
Btw, we could perhaps try permuting arms in combine itself (not in
recog)? In combine we know that there are at most 4 sets (and usually
at most 3), and we also often have a good idea what swaps are likely
to work and which not, so maybe trying just one extra thing will have
good results already.
Segher
