RE: [PATCH] hppa: Improve expansion of ashldi3 when !TARGET_64BIT

[Roger Sayle]

Hi Dave,

It's great to hear from you.  It's been a long while.

Sorry, doh! yes, there's a mistake in my patch (that I introduced when I
renumbered
the operands in the shd's define_expand to be the more logical 0, 1, 2, 3,
then 4).
Sorry for the inconvenience [due to my lack of familiarity with PA-RISC
assembly].
Hopefully you should get much better mileage out of the attached revision.

Thanks again (and my sincere apologies),
Roger
--

-----Original Message-----
From: John David Anglin <dave.ang...@bell.net> 
Sent: 21 August 2020 20:00
To: Roger Sayle <ro...@nextmovesoftware.com>; 'GCC Patches'
<gcc-patches@gcc.gnu.org>
Cc: 'Jeff Law' <l...@redhat.com>
Subject: Re: [PATCH] hppa: Improve expansion of ashldi3 when !TARGET_64BIT

Hi Roger,

On 2020-08-21 8:53 a.m., Roger Sayle wrote:
> I was wondering whether Dave or Jeff (or someone else with access to 
> real hardware) might "spin" this patch for me?
This may be totally unrelated to this patch but I hit this error in stage2
testing your change:
build/genattrtab ../../gcc/gcc/common.md ../../gcc/gcc/config/pa/pa.md
insn-conditions.md \
        -Atmp-attrtab.c -Dtmp-dfatab.c -Ltmp-latencytab.c
genattrtab: Internal error: abort in attr_alt_union, at genattrtab.c:2383

It's great that you are back helpting with the middle-end.

Regards,
Dave

--
John David Anglin  dave.ang...@bell.net


diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 6350c68..713ff17 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -6416,9 +6416,32 @@
   [(set (match_operand:DI 0 "register_operand" "")
        (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
                   (match_operand:DI 2 "arith32_operand" "")))]
-  "TARGET_64BIT"
+  ""
   "
 {
+  if (!TARGET_64BIT)
+    {
+      if (REG_P (operands[0]) && GET_CODE (operands[2]) == CONST_INT)
+       {
+         unsigned HOST_WIDE_INT shift = UINTVAL (operands[2]);
+         if (shift >= 1 && shift <= 31)
+           {
+             rtx dst = operands[0];
+             rtx src = force_reg (DImode, operands[1]);
+             emit_insn (gen_shd_internal (gen_highpart (SImode, dst),
+                                          gen_lowpart (SImode, src),
+                                          GEN_INT (32-shift),
+                                          gen_highpart (SImode, src),
+                                          GEN_INT (shift)));
+             emit_insn (gen_ashlsi3 (gen_lowpart (SImode, dst),
+                                     gen_lowpart (SImode, src),
+                                     GEN_INT (shift)));
+             DONE;
+           }
+       }
+      /* Fallback to using optabs.c's expand_doubleword_shift.  */
+      FAIL;
+    }
   if (GET_CODE (operands[2]) != CONST_INT)
     {
       rtx temp = gen_reg_rtx (DImode);
@@ -6705,6 +6728,15 @@
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
+(define_expand "shd_internal"
+  [(set (match_operand:SI 0 "register_operand")
+       (ior:SI
+         (lshiftrt:SI (match_operand:SI 1 "register_operand")
+                      (match_operand:SI 2 "const_int_operand"))
+         (ashift:SI (match_operand:SI 3 "register_operand")
+                    (match_operand:SI 4 "const_int_operand"))))]
+  "")
+
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
        (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")