Hi Qian, "Qian, Jianhua" <qia...@cn.fujitsu.com> writes: > Hi Richard > >> Would you like the patch to be backported further than GCC 10? > That is good if it could be backported to GCC9.
Sure, now done. >> Does the attached patch to document the addition to GCC 10.3 look OK? > To avoid misunderstanding, could you please remove "for a 512-bit vector > length"? Yeah, that's fine. Here's what I committed to gcc-10/changes.html, with the same wording for gcc-9/changes.html. Thanks, Richard
>From d2f0049d34088519fa28c7c6c1ee62d239523258 Mon Sep 17 00:00:00 2001 From: Richard Sandiford <richard.sandif...@arm.com> Date: Fri, 7 Aug 2020 10:49:23 +0100 Subject: [PATCH] Document A64FX support in GCC 10.3 --- htdocs/gcc-10/changes.html | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index b40f9a57..1a9e3ab7 100644 --- a/htdocs/gcc-10/changes.html +++ b/htdocs/gcc-10/changes.html @@ -1093,6 +1093,23 @@ known to be fixed in the 10.2 release. This list might not be complete (that is, it is possible that some PRs that have been fixed are not listed here).</p> +<!-- .................................................................. --> +<h2 id="GCC10.3">GCC 10.3</h2> + +<h3>Target Specific Changes</h3> + +<h4>AArch64</h4> +<ul> + <li>GCC now supports the Fujitsu A64FX. The associated <code>-mcpu</code> + and <code>-mtune</code> options are <code>-mcpu=a64fx</code> and + <code>-mtune=a64fx</code> respectively. In particular, + <code>-mcpu=a64fx</code> generates code for Armv8.2-A with SVE and + tunes the code for the A64FX. This includes tuning the SVE code, + although by default the code is still length-agnostic and so works for + all SVE implementations. Adding <code>-msve-vector-bits=512</code> + makes the code specific to 512-bit SVE.</li> +</ul> + <!-- .................................................................. --> </body> -- 2.17.1
