PR rtl-optimization/60473 was a code quality regression that has

been cured by improvements to register allocation.  For the function

in the test case, GCC 4.4, 4.5 and 4.6 generated very poor code

requiring two mov instructions:

 

foo:    rdtsc

        mov     rcx, rax

        mov     rax, rdx

        sal     rax, 32

        or      rax, rcx

        ret

 

GCC 4.7 and 4.8 (when the PR was filed) produced better but

still poor code with one mov instruction:

 

foo:    rtdsc

        sal     rdx, 32

        or      rdx, rax

        mov     rax, rdx

        ret

 

Since GCC 4.9 (including current mainline), it generates optimal

code with no mov instructions, matching what used to be generated

in GCC 4.1.

 

foo:    rdtsc

        sal     rdx, 32

        or      rax, rdx

        ret

 

This test case, which has been tested on x86_64-pc-linux-gnu,

simply checks that we don't regress again in future.

Ok for mainline?

 

 

2020-08-02  Roger Sayle  <ro...@nextmovesoftware.com>

 

gcc/testsuite/ChangeLog

PR rtl-optimization/60473

* gcc.target/i386/pr60473.c: New test.

 

Thanks in advance,

Roger

--

Roger Sayle

NextMove Software

Cambridge, UK

 

diff --git a/gcc/testsuite/gcc.target/i386/pr60473.c 
b/gcc/testsuite/gcc.target/i386/pr60473.c
new file mode 100644
index 0000000..6d24ddb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr60473.c
@@ -0,0 +1,12 @@
+/* PR rtl-optimization/60473  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned long long foo()
+{
+  unsigned long long h,l;
+  asm volatile ("rdtsc": "=a" (l), "=d" (h));
+  return l | (h << 32);
+}
+
+/* { dg-final { scan-assembler-not "mov" } } */

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