Hi Carl, On Wed, Jul 08, 2020 at 01:22:33PM -0700, Carl Love wrote: > The following patch adds support for builtins vec_genbm(), vec_genhm(), > vec_genwm(), vec_gendm(), vec_genqm(), vec_cntm(), vec_expandm(), > vec_extractm(). Support for instructions mtvsrbm, mtvsrhm, mtvsrwm, > mtvsrdm, mtvsrqm, cntm, vexpandm, vextractm.
> +;; Mode attribute to give the suffix for the mask instruction > +(define_mode_attr VSX_MM_SUFFIX [(V16QI "b") > + (V8HI "h") > + (V4SI "w") > + (V2DI "d") > + (V1TI "q")]) This could just use <wd>? > +(define_insn "vec_mtvsr_<mode>" > + [(set (match_operand:VSX_MM 0 "altivec_register_operand" "=v") > + (unspec:VSX_MM [(match_operand:DI 1 "gpc_reg_operand" "b")] > + UNSPEC_MTVSBM))] > + "TARGET_POWER10" > + "mtvsr<VSX_MM_SUFFIX>m %0,%1"; > + [(set_attr "type" "vecsimple")]) This can take any "r", not just "b" I think? I.e. r0 is allowed here. The rest looks great. Okay with those tweaks. Thanks! Segher
