On Wed, 2020-07-08 at 09:22 -0700, Carl Love wrote:
> Will, Segher:
>
> I fixed up the patch based on Will's comments. I thought I had made
> and committed the fixes that Will caught, but no.... Sorry about
> that. I will get this right yet.
>
> Carl Love
> -------------------------------------------------------
>
> Version 4
> vec_mtvsrbm was commented out in ver 3. Forgot to go back and actually
> remove it. I was supposed to after testing. It is no longer needed with
> the removal of vec_mtvsrbm_mtvsrbmi. Removed it from ChangeLog.
> Clarification, vec_mtvsrbm_mtvsrbmi was removed in version 3. Updated the
> code to use vec_mtvsr_v16qi instead. Hopefully that clarifies Will's
> comment about "Reworked define_expand vec_mtvsrbm_mtvsrbmi" in version 3.
> Fixed ChangeLog, replaced the FUTURE with P10 that I missed previously.
Don't need to changelog the changelog changes so much, but I'd keep
this part simple, leave the larger story in a paragraph elsewhere if
it's needed. And.. though interesting, we don't always need the
background, just the contents and a call-out for things that changed
wrt previous versions.
This can be simplified to somethinglike
"removed vec_mtvsrbm reference from changelog (v3 change)".
"Updated references to FUTURE_* to match the current P10_*
implementation. "
>
> -----------------------------------------------
> version 3
> rebased onto mainline 7/7/2020
> Change FUTURE to P10 in code and ChangeLog.
> ChangeLog, fixed the name of a couple of files which were wrong.
> Reformated define_mode_attr VSX_MM_SUFFIX definition to shorten the line.
> Reworked define_expand "vec_mtvsrbm_mtvsrbmi" as it will not work as
> intended.
> Changed vsx_register_operand to altivec_register_operand for "v"
> constraint.
> Removed --save-temps from test cases as it is not needed.
> Reran regression testing and ran test cases manually on mambo.
>
> -----------------------------------------------
> version 2
>
> Addressed Will's comments
> - ChangeLog: fixed name/symbol order;
> changed reference from rs6000-c.c to rs6000-builtin.def.
>
> - define_expand "vec_mtvsrbm": changed name to vec_mtvsrbm_mtvsrbmi,
> updated comment
>
> - vsx_mask-runnable.c: divided it up into four smaller test cases,
> vsx_mask-count-runnable.c, vsx_mask-expane-runnable.c,
> vsx_mask-extract-runnable.c, vsx_mask-move-runnable.c.
>
> -------------------------------------------------------
> RS6000 RFC 2629, add VSX mask manipulation support
>
> The following patch adds support for builtins vec_genbm(), vec_genhm(),
> vec_genwm(), vec_gendm(), vec_genqm(), vec_cntm(), vec_expandm(),
> vec_extractm(). Support for instructions mtvsrbm, mtvsrhm, mtvsrwm,
> mtvsrdm, mtvsrqm, cntm, vexpandm, vextractm.
>
> The test has been tested on:
>
> powerpc64le-unknown-linux-gnu (Power 9 LE)
>
> and mambo with no regression errors.
>
> Please let me know if this patch is acceptable for inclusion in the mainline
> branch. Thanks.
>
> Carl Love
> -------------------------------------------------------------------
>
> RS6000, add VSX mask manipulation support
>
> gcc/ChangeLog
>
> 2020-07-07 Carl Love <c...@us.ibm.com>
>
> * config/rs6000/vsx.md (VSX_MM): New define_mode_iterator.
> (VSX_MM4): New define_mode_iterator.
> (VSX_MM_SUFFIX4): New define_mode_attr.
> (vec_mtvsrbmi): New define_insn.
> (vec_mtvsr_<mode>): New define_insn.
> (vec_cntmb_<mode>): New define_insn.
> (vec_extract_<mode>): New define_insn.
> (vec_expand_<mode>): New define_insn.
> (define_c_enum unspec): Add entries UNSPEC_MTVSBM, UNSPEC_VCNTMB,
> UNSPEC_VEXTRACT, UNSPEC_VEXPAND.
> * config/rs6000/altivec.h ( vec_genbm, vec_genhm, vec_genwm,
> vec_gendm, vec_genqm, vec_cntm, vec_expandm, vec_extractm): Add
> defines.
> * config/rs6000/rs6000-builtin.def: Add defines BU_P10_2, BU_P10_1.
> (BU_P10_1): Add definitions for mtvsrbm, mtvsrhm, mtvsrwm,
> mtvsrdm, mtvsrqm, vexpandmb, vexpandmh, vexpandmw, vexpandmd,
> vexpandmq, vextractmb, vextractmh, vextractmw, vextractmd, vextractmq.
> (BU_P10_2): Add definitions for cntmbb, cntmbh, cntmbw, cntmbd.
> (BU_P10_OVERLOAD_1): Add definitions for mtvsrbm, mtvsrhm,
> mtvsrwm, mtvsrdm, mtvsrqm, vexpandm, vextractm.
> (BU_P10_OVERLOAD_2): Add defition for cntm.
> * config/rs6000/rs6000-call.c (rs6000_expand_binop_builtin): Add
> checks for CODE_FOR_vec_cntmbb_v16qi, CODE_FOR_vec_cntmb_v8hi,
> CODE_FOR_vec_cntmb_v4si, CODE_FOR_vec_cntmb_v2di.
> (altivec_overloaded_builtins): Add overloaded argument entries for
> P10_BUILTIN_VEC_MTVSRBM, P10_BUILTIN_VEC_MTVSRHM,
> P10_BUILTIN_VEC_MTVSRWM, P10_BUILTIN_VEC_MTVSRDM,
> P10_BUILTIN_VEC_MTVSRQM, P10_BUILTIN_VEC_VCNTMBB,
> P10_BUILTIN_VCNTMBB, P10_BUILTIN_VCNTMBH,
> P10_BUILTIN_VCNTMBW, P10_BUILTIN_VCNTMBD,
> P10_BUILTIN_VEXPANDMB, P10_BUILTIN_VEXPANDMH,
> P10_BUILTIN_VEXPANDMW, P10_BUILTIN_VEXPANDMD,
> P10_BUILTIN_VEXPANDMQ, P10_BUILTIN_VEXTRACTMB,
> P10_BUILTIN_VEXTRACTMH, P10_BUILTIN_VEXTRACTMW,
> P10_BUILTIN_VEXTRACTMD, P10_BUILTIN_VEXTRACTMQ.
> (builtin_function_type): Add case entries for P10_BUILTIN_MTVSRBM,
> P10_BUILTIN_MTVSRHM, P10_BUILTIN_MTVSRWM, P10_BUILTIN_MTVSRDM,
> P10_BUILTIN_MTVSRQM, P10_BUILTIN_VCNTMBB, P10_BUILTIN_VCNTMBH,
> P10_BUILTIN_VCNTMBW, P10_BUILTIN_VCNTMBD,
> P10_BUILTIN_VEXPANDMB, P10_BUILTIN_VEXPANDMH,
> P10_BUILTIN_VEXPANDMW, P10_BUILTIN_VEXPANDMD,
> P10_BUILTIN_VEXPANDMQ.
> * config/rs6000/rs6000-builtin.def (altivec_overloaded_builtins): Add
> entries for MTVSRBM, MTVSRHM, MTVSRWM, MTVSRDM, MTVSRQM, VCNTM,
> VEXPANDM, VEXTRACTM.
>
> gcc/testsuite/ChangeLog
>
> 2020-07-07 Carl Love <c...@us.ibm.com>
> * gcc.target/powerpc/vsx_mask-count-runnable.c: New test case.
> * gcc.target/powerpc/vsx_mask-expand-runnable.c: New test case.
> * gcc.target/powerpc/vsx_mask-extract-runnable.c: New test case.
> * gcc.target/powerpc/vsx_mask-move-runnable.c: New test case.
> ---
<snip>
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 732a54842b6..a74db0f6f5e 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
<snip>
>
> @@ -5701,3 +5716,55 @@
> "TARGET_POWER10"
> "<xvcvbf16> %x0,%x1"
> [(set_attr "type" "vecfloat")])
> +
> +;; VSX mask manipulation instructions
> +;;;(define_expand "vec_mtvsrbm"
> +;;; [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
> +;;; (unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b")]
> +;;; UNSPEC_MTVSBM))]
> +;;; "TARGET_POWER10"
> +;;; {
> +;;; emit_insn (gen_vec_mtvsr_v16qi (operands[0], operands[1]));
> +;;; DONE;
> +;;;})
> +
Still there.
Thanks,
-Will
