On 6/19/20 2:33 PM, Peter Bergner wrote:
> On 6/19/20 1:12 PM, Segher Boessenkool wrote:
>> On Fri, Jun 19, 2020 at 11:47:35AM -0500, Peter Bergner wrote:
>>>> Why are OImode and XImode handled here?
>>>>
>>>>> static bool
>>>>> rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
>>>>> {
>>>
>>> Do you mean why *aren't* they handled in rs6000_modes_tieable_p?
>>
>> No, this is a comment about the stuff above my comment, so
>>
>>> + /* MMA accumulator modes need FPR registers divisible by 4. We need to
>>> allow
>>> + XImode to have the same registers as PXImode, even though we do not
>>> enable
>>> + the move pattern for XImode. */
>>> + if (mode == PXImode || mode == XImode)
>>> + return (TARGET_MMA && FP_REGNO_P (regno) && (regno & 3) == 0);
Heh, now I'm not so sure after reading the comment before the test. :-)
Mike added this code.
Mike, it looks like you explicitly added XImode here, even though we
will never generate XImode uses. Is there some code somewhere that
requires an integer mode and it's associated partial integer mode to
have the same registers and if they don't, something won't work right?
Meaning, is there some reason I shouldn't remove the XImode use here?
Ditto for OImode and PImode.
Peter
