This test makes sure we do not generate a prefixed instruction with an update
form.
2020-06-01 Michael Meissner <meiss...@linux.ibm.com>
* gcc.target/powerpc/prefix-no-update.c: New test.
---
.../gcc.target/powerpc/prefix-no-update.c | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-no-update.c
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-no-update.c
b/gcc/testsuite/gcc.target/powerpc/prefix-no-update.c
new file mode 100644
index 0000000..e3c2e5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-no-update.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Make sure that we don't generate a prefixed form of the load and store with
+ update instructions (i.e. instead of generating LWZU we have to generate
+ PLWZ plus a PADDI). */
+
+#ifndef SIZE
+#define SIZE 50000
+#endif
+
+struct foo {
+ unsigned int field;
+ char pad[SIZE];
+};
+
+struct foo *inc_load (struct foo *p, unsigned int *q)
+{
+ *q = (++p)->field; /* PLWZ, PADDI, STW. */
+ return p;
+}
+
+struct foo *dec_load (struct foo *p, unsigned int *q)
+{
+ *q = (--p)->field; /* PLWZ, PADDI, STW. */
+ return p;
+}
+
+struct foo *inc_store (struct foo *p, unsigned int *q)
+{
+ (++p)->field = *q; /* LWZ, PADDI, PSTW. */
+ return p;
+}
+
+struct foo *dec_store (struct foo *p, unsigned int *q)
+{
+ (--p)->field = *q; /* LWZ, PADDI, PSTW. */
+ return p;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mplwzu\M} } } */
+/* { dg-final { scan-assembler-not {\mpstwu\M} } } */
+/* { dg-final { scan-assembler-not {\maddis\M} } } */
+/* { dg-final { scan-assembler-not {\maddi\M} } } */
--
1.8.3.1
