Add tests to make sure for -mcpu=future that prefixed load/store instructions
are generated if the offset is larger than 16 bits.
2020-06-01 Michael Meissner <meiss...@linux.ibm.com>
* gcc.target/powerpc/prefix-large-dd.c: New test.
* gcc.target/powerpc/prefix-large-df.c: New test.
* gcc.target/powerpc/prefix-large-di.c: New test.
* gcc.target/powerpc/prefix-large-hi.c: New test.
* gcc.target/powerpc/prefix-large-kf.c: New test.
* gcc.target/powerpc/prefix-large-qi.c: New test.
* gcc.target/powerpc/prefix-large-sd.c: New test.
* gcc.target/powerpc/prefix-large-sf.c: New test.
* gcc.target/powerpc/prefix-large-si.c: New test.
* gcc.target/powerpc/prefix-large-udi.c: New test.
* gcc.target/powerpc/prefix-large-uhi.c: New test.
* gcc.target/powerpc/prefix-large-uqi.c: New test.
* gcc.target/powerpc/prefix-large-usi.c: New test.
* gcc.target/powerpc/prefix-large-v2df.c: New test.
* gcc.target/powerpc/prefix-large.h: Include file for new tests.
---
gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c | 13 ++++++
gcc/testsuite/gcc.target/powerpc/prefix-large-df.c | 13 ++++++
gcc/testsuite/gcc.target/powerpc/prefix-large-di.c | 13 ++++++
gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c | 13 ++++++
gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c | 13 ++++++
gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c | 13 ++++++
gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c | 16 +++++++
gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c | 13 ++++++
gcc/testsuite/gcc.target/powerpc/prefix-large-si.c | 13 ++++++
.../gcc.target/powerpc/prefix-large-udi.c | 14 ++++++
.../gcc.target/powerpc/prefix-large-uhi.c | 14 ++++++
.../gcc.target/powerpc/prefix-large-uqi.c | 14 ++++++
.../gcc.target/powerpc/prefix-large-usi.c | 14 ++++++
.../gcc.target/powerpc/prefix-large-v2df.c | 13 ++++++
gcc/testsuite/gcc.target/powerpc/prefix-large.h | 51 ++++++++++++++++++++++
15 files changed, 240 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-df.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-di.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-si.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/prefix-large.h
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c
new file mode 100644
index 0000000..2000fdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for _Decimal64 objects. */
+
+#define TYPE _Decimal64
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-df.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-df.c
new file mode 100644
index 0000000..48c497b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-df.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for double objects. */
+
+#define TYPE double
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-di.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-di.c
new file mode 100644
index 0000000..aeb879e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-di.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for long objects. */
+
+#define TYPE long
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c
new file mode 100644
index 0000000..965b650
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for short objects. */
+
+#define TYPE short
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplh[az]\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c
new file mode 100644
index 0000000..a2a6330
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for __float128 objects. */
+
+#define TYPE __float128
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c
new file mode 100644
index 0000000..df752ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for signed char objects. */
+
+#define TYPE signed char
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c
new file mode 100644
index 0000000..1c91051
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for _Decimal32 objects. */
+
+#define TYPE _Decimal32
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpaddi\M|\mpli|\mpla\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstfiwx\M} 2 } } */
+
+
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c
new file mode 100644
index 0000000..f534e0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for float objects. */
+
+#define TYPE float
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfs\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstfs\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-si.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-si.c
new file mode 100644
index 0000000..17d5c62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-si.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for int objects. */
+
+#define TYPE int
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplw[az]\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c
new file mode 100644
index 0000000..8edd402
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for unsigned long
+ objects. */
+
+#define TYPE unsigned long
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c
new file mode 100644
index 0000000..5844791
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for unsigned short
+ objects. */
+
+#define TYPE unsigned short
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplhz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c
new file mode 100644
index 0000000..0138503
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for unsigned char
+ objects. */
+
+#define TYPE unsigned char
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c
new file mode 100644
index 0000000..a070a72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for unsigned int
+ objects. */
+
+#define TYPE unsigned int
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplwz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c
b/gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c
new file mode 100644
index 0000000..bb0f95b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+ load/store instruction that has a 34-bit offset for vector objects. */
+
+#define TYPE vector double
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large.h
b/gcc/testsuite/gcc.target/powerpc/prefix-large.h
new file mode 100644
index 0000000..dbc96cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large.h
@@ -0,0 +1,51 @@
+/* Common tests for prefixed instructions testing whether we can generate a
+ 34-bit offset using 1 instruction. */
+
+typedef signed char schar;
+typedef unsigned char uchar;
+typedef unsigned short ushort;
+typedef unsigned int uint;
+typedef unsigned long ulong;
+typedef long double ldouble;
+typedef vector double v2df;
+typedef vector long v2di;
+typedef vector float v4sf;
+typedef vector int v4si;
+
+#ifndef TYPE
+#define TYPE ulong
+#endif
+
+#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET)
+#define DO_ADD 1
+#define DO_VALUE 1
+#define DO_SET 1
+#endif
+
+#ifndef CONSTANT
+#define CONSTANT 0x123450UL
+#endif
+
+#if DO_ADD
+void
+add (TYPE *p, TYPE a)
+{
+ p[CONSTANT] += a;
+}
+#endif
+
+#if DO_VALUE
+TYPE
+value (TYPE *p)
+{
+ return p[CONSTANT];
+}
+#endif
+
+#if DO_SET
+void
+set (TYPE *p, TYPE a)
+{
+ p[CONSTANT] = a;
+}
+#endif
--
1.8.3.1
