On Tue, 26 May 2020, Jim Wilson wrote: > On Tue, May 26, 2020 at 12:12 AM Richard Biener <rguent...@suse.de> wrote: > > From a look at the series description below you seem to add a new way > > of doing loads for this. Did you review other ISAs (those I'm not > > familiar with myself too much are SVE, RISC-V and GCN) in GCC whether > > they have similar support and whether your approach can be supported > > there? ISTR SVE must have some similar support - what's the reason > > you do not piggy-back on that? > > There isn't any RISC-V Vector support in GCC yet. The RVV spec is > still in draft and still occasionally changing in incompatible ways. > We've done some experimenting with gcc patches, but all we have are > intrinsics. We haven't implemented any auto vectorization support, so > we haven't defined tree representations for anything yet, other than > the types we need for intrinsics support. But if it looks OK for SVE > then it probably will be OK for RVV.
Btw, I'm specifically looking for other load/store with length implementations and as to whether they agree on taking bytes for the length rather than, for example the number of lanes. I guess exposing this detail on GIMPLE can help IV selection but if we'd ever get a differing semantics ISA we'd have to add another set of IFNs, so maybe the PPC ones should be named in a more specific way like _WITH_BYTES or _BYTES or _WITH_BYTE_LENGTH or so to allow _WITH_LANES? Richard. > Jim > -- Richard Biener <rguent...@suse.de> SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg, Germany; GF: Felix Imendörffer; HRB 36809 (AG Nuernberg)
