On Tue, May 26, 2020 at 12:12 AM Richard Biener <rguent...@suse.de> wrote: > From a look at the series description below you seem to add a new way > of doing loads for this. Did you review other ISAs (those I'm not > familiar with myself too much are SVE, RISC-V and GCN) in GCC whether > they have similar support and whether your approach can be supported > there? ISTR SVE must have some similar support - what's the reason > you do not piggy-back on that?
There isn't any RISC-V Vector support in GCC yet. The RVV spec is still in draft and still occasionally changing in incompatible ways. We've done some experimenting with gcc patches, but all we have are intrinsics. We haven't implemented any auto vectorization support, so we haven't defined tree representations for anything yet, other than the types we need for intrinsics support. But if it looks OK for SVE then it probably will be OK for RVV. Jim
