Complement commit bfe78b08471f ("RISC-V: Using fmv.x.w/fmv.w.x rather
than fmv.x.s/fmv.s.x") and document a binutils 2.30 requirement in the
installation manual, matching the addition of fmv.x.w/fmv.w.x mnemonics
to GAS.
gcc/
* doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
<riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
2.30.
---
On Wed, 18 Mar 2020, Maciej W. Rozycki wrote:
> > > At the very least I think we ought to document the minimum version of
> > > binutils now required by GCC for RISC-V support.
> >
> > The new opcodes were added to gas in 2017-09-27, and I can't recommend
> > using any binutils or gcc release that predates 2018-01-01 because
> > they are all known to be buggy, or incompatible with the current ISA
> > definition. So I don't see any need for a configure test for this
> > change. Anyone missing the new instructions in gas has bigger
> > problems to worry about.
[...]
> Our installation instructions state binutils 2.28 as the requirement for
> all the RISC-V targets, however the change for fmv.x.w/fmv.w.x instruction
> support was only added in the binutils 2.30 development cycle.
Here's the resulting change. Verified with `make info' and `make check'.
OK to apply?
Maciej
---
gcc/doc/install.texi | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
gcc-riscv-binutils-version.diff
Index: gcc/gcc/doc/install.texi
===================================================================
--- gcc.orig/gcc/doc/install.texi
+++ gcc/gcc/doc/install.texi
@@ -4545,8 +4545,7 @@ This configuration is intended for embed
@heading riscv32-*-elf
The RISC-V RV32 instruction set.
This configuration is intended for embedded systems.
-This (and all other RISC-V) targets are supported upstream as of the
-binutils 2.28 release.
+This (and all other RISC-V) targets require the binutils 2.30 release.
@html
<hr />
@@ -4554,8 +4553,7 @@ binutils 2.28 release.
@anchor{riscv32-x-linux}
@heading riscv32-*-linux
The RISC-V RV32 instruction set running GNU/Linux.
-This (and all other RISC-V) targets are supported upstream as of the
-binutils 2.28 release.
+This (and all other RISC-V) targets require the binutils 2.30 release.
@html
<hr />
@@ -4564,8 +4562,7 @@ binutils 2.28 release.
@heading riscv64-*-elf
The RISC-V RV64 instruction set.
This configuration is intended for embedded systems.
-This (and all other RISC-V) targets are supported upstream as of the
-binutils 2.28 release.
+This (and all other RISC-V) targets require the binutils 2.30 release.
@html
<hr />
@@ -4573,8 +4570,7 @@ binutils 2.28 release.
@anchor{riscv64-x-linux}
@heading riscv64-*-linux
The RISC-V RV64 instruction set running GNU/Linux.
-This (and all other RISC-V) targets are supported upstream as of the
-binutils 2.28 release.
+This (and all other RISC-V) targets require the binutils 2.30 release.
@html
<hr />
