[PATCH] RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x

[Kito Cheng]

 - fmv.x.s/fmv.s.x renamed to fmv.x.w/fmv.w.x in the latest RISC-V ISA
   manual.

 - Tested rv32gc/rv64gc on bare-metal with qemu.

ChangeLog

gcc/

Kito Cheng  <kito.ch...@sifive.com>

        * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
        rather than fmv.x.s/fmv.s.x.
---
 gcc/config/riscv/riscv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index ee51ad7ce1e..5ef74acb56d 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1917,7 +1917,7 @@ riscv_output_move (rtx dest, rtx src)
   if (dest_code == REG && GP_REG_P (REGNO (dest)))
     {
       if (src_code == REG && FP_REG_P (REGNO (src)))
-       return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1";
+       return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1";
 
       if (src_code == MEM)
        switch (GET_MODE_SIZE (mode))
@@ -1954,7 +1954,7 @@ riscv_output_move (rtx dest, rtx src)
          if (FP_REG_P (REGNO (dest)))
            {
              if (!dbl_p)
-               return "fmv.s.x\t%0,%z1";
+               return "fmv.w.x\t%0,%z1";
              if (TARGET_64BIT)
                return "fmv.d.x\t%0,%z1";
              /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
-- 
2.25.0