Hi,
Here is the latest version of the patch. That test should now work.
Thanks,
Delia
On 3/5/20 11:06 AM, Richard Sandiford wrote:
Hi,
Thanks for the update and sorry for the slow reply.
When I try the patch locally I get:
FAIL: gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c -O0 (test for
excess errors)
FAIL: gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c -O1 (test for
excess errors)
FAIL: gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c -O2 (test for
excess errors)
FAIL: gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c -O2 -flto
-fno-use-linker-plugin -flto-partition=none (test for excess errors)
FAIL: gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects (test for excess errors)
FAIL: gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c -O3 -g (test for
excess errors)
FAIL: gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c -Og -g (test for
excess errors)
FAIL: gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c -Os (test for
excess errors)
I think that's because:
Delia Burduv <delia.bur...@arm.com> writes:
diff --git a/gcc/config/aarch64/arm_bf16.h b/gcc/config/aarch64/arm_bf16.h
index
3759c0d1cb449a7f0125cc2a1433127564d66622..fa7080c2953bc3254f01d842a8afef917d469080
100644
--- a/gcc/config/aarch64/arm_bf16.h
+++ b/gcc/config/aarch64/arm_bf16.h
@@ -27,6 +27,19 @@
#ifndef _AARCH64_BF16_H_
#define _AARCH64_BF16_H_
+#pragma GCC push_options
+#pragma GCC target ("+nothing+bf16")
+
typedef __bf16 bfloat16_t;
+typedef float float32_t;
+
+__extension__ extern __inline bfloat16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcvth_bf16_f32 (float32_t __a)
+{
+ return __builtin_aarch64_bfcvtbf (__a);
+}
+
+#pragma GCC pop_options
"+bf16" implicitly enables "+simd", so functions guarded with
"+nothing+bf16" are only available when "+simd" is available.
I think we want "+nothing+bf16+nosimd" instead. (Haven't tested
that though.)
Very minor, but: it might be clearer to leave the typedefs outside
of the #pragma block. It doesn't make any difference to the behaviour,
but it emphasises that the typedefs really are available unconditionally.
Looks ready to go otherwise.
Thanks,
Richard
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index d8bb96f8ed60648477f952ea6b88eae67cc9c921..cc0bd0e6b592528e4b1559e9a3f5b0153511dffd 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -714,3 +714,9 @@
VAR1 (TERNOP, simd_smmla, 0, v16qi)
VAR1 (TERNOPU, simd_ummla, 0, v16qi)
VAR1 (TERNOP_SSUS, simd_usmmla, 0, v16qi)
+
+ /* Implemented by aarch64_bfcvtn{q}{2}<mode> */
+ VAR1 (UNOP, bfcvtn, 0, v4bf)
+ VAR1 (UNOP, bfcvtn_q, 0, v8bf)
+ VAR1 (BINOP, bfcvtn2, 0, v8bf)
+ VAR1 (UNOP, bfcvt, 0, bf)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 89aaf8c018e3340dd2d53fc2a6538d3d1220b103..035f3163223d0b618fa28beb007f2f70c7d6c060 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -7207,3 +7207,32 @@
"<sur>mmla\\t%0.4s, %2.16b, %3.16b"
[(set_attr "type" "neon_mla_s_q")]
)
+
+;; bfcvtn
+(define_insn "aarch64_bfcvtn<q><mode>"
+ [(set (match_operand:V4SF_TO_BF 0 "register_operand" "=w")
+ (unspec:V4SF_TO_BF [(match_operand:V4SF 1 "register_operand" "w")]
+ UNSPEC_BFCVTN))]
+ "TARGET_BF16_SIMD"
+ "bfcvtn\\t%0.4h, %1.4s"
+ [(set_attr "type" "neon_fp_cvt_narrow_s_q")]
+)
+
+(define_insn "aarch64_bfcvtn2v8bf"
+ [(set (match_operand:V8BF 0 "register_operand" "=w")
+ (unspec:V8BF [(match_operand:V8BF 1 "register_operand" "0")
+ (match_operand:V4SF 2 "register_operand" "w")]
+ UNSPEC_BFCVTN2))]
+ "TARGET_BF16_SIMD"
+ "bfcvtn2\\t%0.8h, %2.4s"
+ [(set_attr "type" "neon_fp_cvt_narrow_s_q")]
+)
+
+(define_insn "aarch64_bfcvtbf"
+ [(set (match_operand:BF 0 "register_operand" "=w")
+ (unspec:BF [(match_operand:SF 1 "register_operand" "w")]
+ UNSPEC_BFCVT))]
+ "TARGET_BF16_FP"
+ "bfcvt\\t%h0, %s1"
+ [(set_attr "type" "f_cvt")]
+)
diff --git a/gcc/config/aarch64/arm_bf16.h b/gcc/config/aarch64/arm_bf16.h
index 3759c0d1cb449a7f0125cc2a1433127564d66622..984875dcc014300c489209c11abf41b1c47b7fbe 100644
--- a/gcc/config/aarch64/arm_bf16.h
+++ b/gcc/config/aarch64/arm_bf16.h
@@ -28,5 +28,18 @@
#define _AARCH64_BF16_H_
typedef __bf16 bfloat16_t;
+typedef float float32_t;
+
+#pragma GCC push_options
+#pragma GCC target ("+nothing+bf16+nosimd")
+
+__extension__ extern __inline bfloat16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcvth_bf16_f32 (float32_t __a)
+{
+ return __builtin_aarch64_bfcvtbf (__a);
+}
+
+#pragma GCC pop_options
#endif
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index b6f42ac630295d9b827e2763cf487ccfb5bfe64b..cc4ce76d16e6cb2451f384b7ede7c26bdb22d614 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -35634,6 +35634,27 @@ vbfmlaltq_laneq_f32 (float32x4_t __r, bfloat16x8_t __a, bfloat16x8_t __b,
return __builtin_aarch64_bfmlalt_lane_qv4sf (__r, __a, __b, __index);
}
+__extension__ extern __inline bfloat16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcvt_bf16_f32 (float32x4_t __a)
+{
+ return __builtin_aarch64_bfcvtnv4bf (__a);
+}
+
+__extension__ extern __inline bfloat16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcvtq_low_bf16_f32 (float32x4_t __a)
+{
+ return __builtin_aarch64_bfcvtn_qv8bf (__a);
+}
+
+__extension__ extern __inline bfloat16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcvtq_high_bf16_f32 (bfloat16x8_t __inactive, float32x4_t __a)
+{
+ return __builtin_aarch64_bfcvtn2v8bf (__inactive, __a);
+}
+
#pragma GCC pop_options
/* AdvSIMD 8-bit Integer Matrix Multiply (I8MM) intrinsics. */
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index ec1b92c5379f7c33446d0ac3556f6358fb7433d3..b56a050ac09b6482933203008fc834ce2b6ec5c1 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -462,6 +462,9 @@
;; SVE predicate modes that control 16-bit, 32-bit or 64-bit elements.
(define_mode_iterator PRED_HSD [VNx8BI VNx4BI VNx2BI])
+;; Bfloat16 modes to which V4SF can be converted
+(define_mode_iterator V4SF_TO_BF [V4BF V8BF])
+
;; ------------------------------------------------------------------
;; Unspec enumerations for Advance SIMD. These could well go into
;; aarch64.md but for their use in int_iterators here.
@@ -828,6 +831,9 @@
UNSPEC_BFMLALB ; Used in aarch64-sve.md.
UNSPEC_BFMLALT ; Used in aarch64-sve.md.
UNSPEC_BFMMLA ; Used in aarch64-sve.md.
+ UNSPEC_BFCVTN ; Used in aarch64-simd.md.
+ UNSPEC_BFCVTN2 ; Used in aarch64-simd.md.
+ UNSPEC_BFCVT ; Used in aarch64-simd.md.
])
;; ------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c
new file mode 100644
index 0000000000000000000000000000000000000000..bbea630b1820d578bdf1619834f29b919f5c3f32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c
@@ -0,0 +1,48 @@
+/* { dg-do assemble { target { aarch64*-*-* } } } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-save-temps" } */
+/* { dg-final { check-function-bodies "**" "" {-O[^0]} } } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+#include <arm_neon.h>
+
+/*
+**test_bfcvtn:
+** bfcvtn v0.4h, v0.4s
+** ret
+*/
+bfloat16x4_t test_bfcvtn (float32x4_t a)
+{
+ return vcvt_bf16_f32 (a);
+}
+
+/*
+**test_bfcvtnq:
+** bfcvtn v0.4h, v0.4s
+** ret
+*/
+bfloat16x8_t test_bfcvtnq (float32x4_t a)
+{
+ return vcvtq_low_bf16_f32 (a);
+}
+
+/*
+**test_bfcvtnq2:
+** bfcvtn2 v0.8h, v1.4s
+** ret
+*/
+bfloat16x8_t test_bfcvtnq2 (bfloat16x8_t inactive, float32x4_t a)
+{
+ return vcvtq_high_bf16_f32 (inactive, a);
+}
+
+/*
+**test_bfcvt:
+** bfcvt h0, s0
+** ret
+*/
+bfloat16_t test_bfcvt (float32_t a)
+{
+ return vcvth_bf16_f32 (a);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nobf16.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nobf16.c
new file mode 100644
index 0000000000000000000000000000000000000000..9904d65f9148debc1a1e147d75e5c54fb0f9da71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nobf16.c
@@ -0,0 +1,10 @@
+/* { dg-do assemble { target { aarch64*-*-* } } } */
+/* { dg-additional-options "-march=armv8.2-a+nobf16" } */
+
+#include <arm_neon.h>
+
+bfloat16_t test_bfcvt (float32_t a)
+{
+ /* { dg-error "inlining failed .* 'vcvth_bf16_f32" "" { target *-*-* } 0 } */
+ return vcvth_bf16_f32 (a);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c
new file mode 100644
index 0000000000000000000000000000000000000000..1da230b988c33832a791f0cc23553f3e6889099e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble { target { aarch64*-*-* } } } */
+/* { dg-require-effective-target aarch64_asm_bf16_ok } */
+/* { dg-additional-options "-save-temps -march=armv8.2-a+bf16+nosimd" } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include <arm_neon.h>
+
+/*
+**test_bfcvt:
+** bfcvt h0, s0
+** ret
+*/
+bfloat16_t test_bfcvt (float32_t a)
+{
+ return vcvth_bf16_f32 (a);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtn-nobf16.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtn-nobf16.c
new file mode 100644
index 0000000000000000000000000000000000000000..b3b6db12358677b2f34169214241318e5d0d764f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtn-nobf16.c
@@ -0,0 +1,10 @@
+/* { dg-do assemble { target { aarch64*-*-* } } } */
+/* { dg-additional-options "-march=armv8.2-a+nobf16" } */
+
+#include <arm_neon.h>
+
+bfloat16x4_t test_bfcvtn (float32x4_t a)
+{
+ /* { dg-error "inlining failed .* 'vcvt_bf16_f32" "" { target *-*-* } 0 } */
+ return vcvt_bf16_f32 (a);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c
new file mode 100644
index 0000000000000000000000000000000000000000..4b730e39d4ec2fb680235a61cc0a6d16a8ac4cad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble { target { aarch64*-*-* } } } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-save-temps" } */
+/* { dg-final { check-function-bodies "**" "" {-O[^0]} } } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+#include <arm_neon.h>
+
+/*
+**test_bfcvtnq2_untied:
+** mov v0.16b, v1.16b
+** bfcvtn2 v0.8h, v2.4s
+** ret
+*/
+bfloat16x8_t test_bfcvtnq2_untied (bfloat16x8_t unused, bfloat16x8_t inactive,
+ float32x4_t a)
+{
+ return vcvtq_high_bf16_f32 (inactive, a);
+}
