[PATCH 11/46] i386: Emulate MMX ashr3/3 with SSE

[H.J. Lu]

Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE.  Only SSE register
source operand is allowed.

        PR target/89021
        * config/i386/mmx.md (ashr<mode>3): New.
        (<shift_insn><mode>3): Likewise.
---
 gcc/config/i386/mmx.md | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index fe199b84935..0b2383ef764 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1012,6 +1012,40 @@
        (const_string "0")))
    (set_attr "mode" "DI")])
 
+(define_insn "ashr<mode>3"
+  [(set (match_operand:MMXMODE24 0 "register_operand" "=Yx,Yy")
+        (ashiftrt:MMXMODE24
+         (match_operand:MMXMODE24 1 "register_operand" "0,Yy")
+         (match_operand:DI 2 "nonmemory_operand" "YxN,YyN")))]
+  "TARGET_MMX_WITH_SSE"
+  "@
+   psra<mmxvecsize>\t{%2, %0|%0, %2}
+   vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft,sseishft")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand")
+       (const_string "1")
+       (const_string "0")))
+   (set_attr "mode" "TI")])
+
+(define_insn "<shift_insn><mode>3"
+  [(set (match_operand:MMXMODE248 0 "register_operand" "=Yx,Yy")
+        (any_lshift:MMXMODE248
+         (match_operand:MMXMODE248 1 "register_operand" "0,Yy")
+         (match_operand:DI 2 "nonmemory_operand" "YxN,YyN")))]
+  "TARGET_MMX_WITH_SSE"
+  "@
+   p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
+   vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft,sseishft")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand")
+       (const_string "1")
+       (const_string "0")))
+   (set_attr "mode" "TI")])
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel integral comparisons
-- 
2.20.1