Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for INT andnot operations.
gcc/
PR target/72782
* config/i386/sse.md (*andnot<mode>3_bst): New.
gcc/testsuite/
PR target/72782
* gcc.target/i386/avx512f-andn-di-zmm-1.c: New test.
* gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise.
---
gcc/config/i386/sse.md | 13 +++++++++++++
.../gcc.target/i386/avx512f-andn-di-zmm-1.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-1.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-2.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-3.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-4.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-5.c | 12 ++++++++++++
.../gcc.target/i386/avx512vl-andn-si-xmm-1.c | 12 ++++++++++++
.../gcc.target/i386/avx512vl-andn-si-ymm-1.c | 12 ++++++++++++
9 files changed, 109 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 29f390ead1f..05bd5781804 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -12070,6 +12070,19 @@
]
(const_string "<sseinsnmode>")))])
+(define_insn "*andnot<mode>3_bst"
+ [(set (match_operand:VI 0 "register_operand" "=v")
+ (and:VI
+ (not:VI48_AVX512VL
+ (match_operand:VI48_AVX512VL 1 "register_operand" "v"))
+ (vec_duplicate:VI48_AVX512VL
+ (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
+ "TARGET_AVX512F"
+ "vpandn<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_insn "*andnot<mode>3_mask"
[(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI48_AVX512VL
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
new file mode 100644
index 00000000000..1450d3c1914
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnq\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
new file mode 100644
index 00000000000..c9d8a820295
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
new file mode 100644
index 00000000000..a9608ca095d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } }
*/
+/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
new file mode 100644
index 00000000000..71751fc874c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } }
*/
+/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
new file mode 100644
index 00000000000..d74c373d435
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } }
*/
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+%zmm\[0-9\]+,
%zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
new file mode 100644
index 00000000000..8211815dbbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[
\\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
new file mode 100644
index 00000000000..0b084ae5f7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#include <immintrin.h>
+
+__m128i
+foo (__m128i x, int *f)
+{
+ return (__m128i) (~(__v4su) x & (__v4su) _mm_set1_epi32 (*f));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
new file mode 100644
index 00000000000..cd27b40ba44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#include <immintrin.h>
+
+__m256i
+foo (__m256i x, int *f)
+{
+ return (__m256i) (~(__v8su) x & (__v8su) _mm256_set1_epi32 (*f));
+}
--
2.17.2
