Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for INT add operations.
gcc/
PR target/72782
* config/i386/sse.md (avx512bcst): Updated for V4SI, V2DI, V8SI,
V4DI, V16SI and V8DI.
(*minus<mode>3<mask_name>_bcst): New.
(*plus<mode>3<mask_name>_bcst): Likewise.
gcc/testsuite/
PR target/72782
* gcc.target/i386/avx512f-add-di-zmm-1.c: New test.
* gcc.target/i386/avx512f-add-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-6.c: Likewise.
* gcc.target/i386/avx512f-sub-di-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512vl-add-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-add-si-ymm-1.c: Likewise.
* gcc.target/i386/avx512vl-sub-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-sub-si-ymm-1.c: Likewise.
---
gcc/config/i386/sse.md | 29 ++++++++++++++++++-
.../gcc.target/i386/avx512f-add-di-zmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-2.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-3.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-4.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-5.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-6.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-di-zmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-2.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-3.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-4.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-5.c | 12 ++++++++
.../gcc.target/i386/avx512vl-add-si-xmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512vl-add-si-ymm-1.c | 12 ++++++++
.../gcc.target/i386/avx512vl-sub-si-xmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512vl-sub-si-ymm-1.c | 12 ++++++++
18 files changed, 232 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 2c702ceed2d..2d4fac3f8f7 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -660,7 +660,10 @@
V16SF V8DF])
(define_mode_attr avx512bcst
- [(V4SF "%{1to4%}") (V2DF "%{1to2%}")
+ [(V4SI "%{1to4%}") (V2DI "%{1to2%}")
+ (V8SI "%{1to8%}") (V4DI "%{1to4%}")
+ (V16SI "%{1to16%}") (V8DI "%{1to8%}")
+ (V4SF "%{1to4%}") (V2DF "%{1to2%}")
(V8SF "%{1to8%}") (V4DF "%{1to4%}")
(V16SF "%{1to16%}") (V8DF "%{1to8%}")])
@@ -10408,6 +10411,30 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<sseinsnmode>")])
+(define_insn "*sub<mode>3_bcst"
+ [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
+ (minus:VI48_AVX512VL
+ (match_operand:VI48_AVX512VL 1 "register_operand" "v")
+ (vec_duplicate:VI48_AVX512VL
+ (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
+ "TARGET_AVX512F && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "vpsub<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
+ [(set_attr "type" "sseiadd")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "*plus<mode>3_bcst"
+ [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
+ (plus:VI48_AVX512VL
+ (vec_duplicate:VI48_AVX512VL
+ (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
+ (match_operand:VI48_AVX512VL 2 "register_operand" "v")))]
+ "TARGET_AVX512F && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ "vpadd<ssemodesuffix>\t{%1<avx512bcst>, %2, %0|%0, %2, %1<avx512bcst>}"
+ [(set_attr "type" "sseiadd")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_insn "*<plusminus_insn><mode>3_mask"
[(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI48_AVX512VL
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
new file mode 100644
index 00000000000..eaf5093b9c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddq\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
new file mode 100644
index 00000000000..bdb5a1802cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
new file mode 100644
index 00000000000..de2148dbf53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
new file mode 100644
index 00000000000..b581f8afefa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } }
*/
+/* { dg-final { scan-assembler-times "vpaddd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
new file mode 100644
index 00000000000..04f199fd1ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } }
*/
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+%zmm\[0-9\]+,
%zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
new file mode 100644
index 00000000000..983d3906664
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[
\\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
new file mode 100644
index 00000000000..54dba2b3f73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[
\\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-6.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
new file mode 100644
index 00000000000..771f23df57a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpsubq\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
new file mode 100644
index 00000000000..3e4897c4a8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpsubd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
new file mode 100644
index 00000000000..090f3ffbe62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } }
*/
+/* { dg-final { scan-assembler-times "vpsubd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
new file mode 100644
index 00000000000..1f75c88c3ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } }
*/
+/* { dg-final { scan-assembler-times "vpsubd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
new file mode 100644
index 00000000000..0617a7b151b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } }
*/
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+%zmm\[0-9\]+,
%zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
new file mode 100644
index 00000000000..4e0c8451ac2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpsubd\[
\\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
new file mode 100644
index 00000000000..bf57563337e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#define type __m128i
+#define vec
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
new file mode 100644
index 00000000000..54bdbebb20c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#define type __m256i
+#define vec 256
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
new file mode 100644
index 00000000000..a29a2366a4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpsubd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#define type __m128i
+#define vec
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
new file mode 100644
index 00000000000..3f248a3c08f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpsubd\[
\\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#define type __m256i
+#define vec 256
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
--
2.17.2
