This is a fallout of the consolidation patch for floating-point insns. When
the regular and no_fpu patterns for movdf were merged, the r/ro alternative of
the latter pattern was merged with the r/rFo alternative of the former. This
was presumably intended, but the associated splitter wasn't changed, so the
r/F case breaks with -mno-fpu/-msoft-float.
Fixed thusly. The patch also reindents some contraints (and a reindentation
patch is also attached for the 4.6 branch so as to make comparisons easier).
Bootstrapped/regtested on SPARC/Solaris, applied on mainline (and 4.6 branch).
2011-11-02 Eric Botcazou <ebotca...@adacore.com>
PR target/50945
* config/sparc/sparc.md (movsf_insn): Reindent constraints.
(movdf_insn_sp32): Likewise. Remove redundant G constraint.
(movdf_insn_sp64): Likewise.
(DFmode splitter): Do not test TARGET_FPU.
(movtf_insn_sp32): Reindent constraints.
(movtf_insn_sp32_no_fpu): Likewise.
(movtf_insn_sp64): Likewise.
(movtf_insn_sp64_hq): Likewise.
(movtf_insn_sp64_no_fpu): Likewise.
2011-11-02 Eric Botcazou <ebotca...@adacore.com>
* gcc.target/sparc/20111102-1.c: New test.
--
Eric Botcazou
Index: config/sparc/sparc.md
===================================================================
--- config/sparc/sparc.md (revision 180732)
+++ config/sparc/sparc.md (working copy)
@@ -2041,8 +2041,8 @@ (define_expand "movsf"
})
(define_insn "*movsf_insn"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,f, *r,*r,*r,*r, f, f,*r, m, m")
- (match_operand:SF 1 "input_operand" "G,C,f,*rR, Q, S, f,*r, m, m, f,*rG"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,f, *r,*r,*r,*r, f,f,*r,m, m")
+ (match_operand:SF 1 "input_operand" "G,C,f,*rR, Q, S, f,*r,m, m,f,*rG"))]
"(register_operand (operands[0], SFmode)
|| register_or_zero_or_all_ones_operand (operands[1], SFmode))"
{
@@ -2138,8 +2138,8 @@ (define_expand "movdf"
})
(define_insn "*movdf_insn_sp32"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f, e,T,W,U,T, f, *r, o,o")
- (match_operand:DF 1 "input_operand" "G,C,e,e, f,*r,W#F,G,e,T,U,o#F,*roGF,*rG,f"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f, e,T,W,U,T, f, *r, o,o")
+ (match_operand:DF 1 "input_operand" "G,C,e,e, f,*r,W#F,G,e,T,U,o#F,*roF,*rG,f"))]
"! TARGET_ARCH64
&& (register_operand (operands[0], DFmode)
|| register_or_zero_or_all_ones_operand (operands[1], DFmode))"
@@ -2166,7 +2166,7 @@ (define_insn "*movdf_insn_sp32"
(define_insn "*movdf_insn_sp64"
[(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,*r, e, e,W, *r,*r, m,*r")
- (match_operand:DF 1 "input_operand" "G,C,e, e,*r,W#F,e,*rG, m,*rG, F"))]
+ (match_operand:DF 1 "input_operand" "G,C,e, e,*r,W#F,e,*rG, m,*rG, F"))]
"TARGET_ARCH64
&& (register_operand (operands[0], DFmode)
|| register_or_zero_or_all_ones_operand (operands[1], DFmode))"
@@ -2191,9 +2191,8 @@ (define_insn "*movdf_insn_sp64"
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "const_double_operand" ""))]
- "TARGET_FPU
- && (GET_CODE (operands[0]) == REG
- && SPARC_INT_REG_P (REGNO (operands[0])))
+ "REG_P (operands[0])
+ && SPARC_INT_REG_P (REGNO (operands[0]))
&& ! const_zero_operand (operands[1], GET_MODE (operands[0]))
&& reload_completed"
[(clobber (const_int 0))]
@@ -2378,8 +2377,8 @@ (define_expand "movtf"
})
(define_insn "*movtf_insn_sp32"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,U,r")
- (match_operand:TF 1 "input_operand" "G,oe,GeUr,o,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o,U, r")
+ (match_operand:TF 1 "input_operand" " G,oe,GeUr,o,roG"))]
"TARGET_FPU
&& ! TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
@@ -2392,8 +2391,8 @@ (define_insn "*movtf_insn_sp32"
;; when -mno-fpu.
(define_insn "*movtf_insn_sp32_no_fpu"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
- (match_operand:TF 1 "input_operand" "G,o,U,roG,r"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o, r,o")
+ (match_operand:TF 1 "input_operand" " G,o,U,roG,r"))]
"! TARGET_FPU
&& ! TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
@@ -2402,8 +2401,8 @@ (define_insn "*movtf_insn_sp32_no_fpu"
[(set_attr "length" "4")])
(define_insn "*movtf_insn_sp64"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,r")
- (match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o, r")
+ (match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
"TARGET_FPU
&& TARGET_ARCH64
&& ! TARGET_HARD_QUAD
@@ -2413,8 +2412,8 @@ (define_insn "*movtf_insn_sp64"
[(set_attr "length" "2")])
(define_insn "*movtf_insn_sp64_hq"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m,o,r")
- (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m, o, r")
+ (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
"TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
@@ -2431,8 +2430,8 @@ (define_insn "*movtf_insn_sp64_hq"
(set_attr "length" "2,*,*,*,2,2")])
(define_insn "*movtf_insn_sp64_no_fpu"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
- (match_operand:TF 1 "input_operand" "orG,rG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "= r, o")
+ (match_operand:TF 1 "input_operand" "orG,rG"))]
"! TARGET_FPU
&& TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
/* PR target/50945 */
/* { dg-do compile } */
/* { dg-options "-O -msoft-float" } */
double
__powidf2 (double x, int m)
{
unsigned int n = m < 0 ? -m : m;
double y = n % 2 ? x : 1;
while (n >>= 1)
{
x = x * x;
if (n % 2)
y = y * x;
}
return m < 0 ? 1/y : y;
}
Index: config/sparc/sparc.md
===================================================================
--- config/sparc/sparc.md (revision 180307)
+++ config/sparc/sparc.md (working copy)
@@ -1813,8 +1813,8 @@ (define_expand "mov<V32:mode>"
})
(define_insn "*movsf_insn"
- [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,*r,*r,*r,f,*r,m,m")
- (match_operand:V32 1 "input_operand" "GY,f,*rRY,Q,S,m,m,f,*rGY"))]
+ [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f, *r,*r,*r,f,*r,m, m")
+ (match_operand:V32 1 "input_operand" "GY,f,*rRY, Q, S,m, m,f,*rGY"))]
"TARGET_FPU
&& (register_operand (operands[0], <V32:MODE>mode)
|| register_or_zero_operand (operands[1], <V32:MODE>mode))"
@@ -1861,8 +1861,8 @@ (define_insn "*movsf_insn"
;; when -mno-fpu.
(define_insn "*movsf_insn_no_fpu"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,m")
- (match_operand:SF 1 "input_operand" "rR,Q,S,m,rG"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r, m")
+ (match_operand:SF 1 "input_operand" "rR,Q,S,m,rG"))]
"! TARGET_FPU
&& (register_operand (operands[0], SFmode)
|| register_or_zero_operand (operands[1], SFmode))"
@@ -1948,8 +1948,8 @@ (define_expand "mov<V64:mode>"
;; Be careful, fmovd does not exist when !v9.
(define_insn "*movdf_insn_sp32"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o")
- (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "= e,W,U,T,o,e, *r, o, e,o")
+ (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
"TARGET_FPU
&& ! TARGET_V9
&& (register_operand (operands[0], DFmode)
@@ -1969,8 +1969,8 @@ (define_insn "*movdf_insn_sp32"
(set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
(define_insn "*movdf_insn_sp32_no_fpu"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
- (match_operand:DF 1 "input_operand" "T,U,G,ro,r"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o, r,o")
+ (match_operand:DF 1 "input_operand" " T,U,G,ro,r"))]
"! TARGET_FPU
&& ! TARGET_V9
&& (register_operand (operands[0], DFmode)
@@ -1986,8 +1986,8 @@ (define_insn "*movdf_insn_sp32_no_fpu"
;; We have available v9 double floats but not 64-bit integer registers.
(define_insn "*movdf_insn_sp32_v9"
- [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o")
- (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))]
+ [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e, e, T,W,U,T, f, *r, o")
+ (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roFD,*rGYf"))]
"TARGET_FPU
&& TARGET_V9
&& ! TARGET_ARCH64
@@ -2009,8 +2009,8 @@ (define_insn "*movdf_insn_sp32_v9"
(set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
(define_insn "*movdf_insn_sp32_v9_no_fpu"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
- (match_operand:DF 1 "input_operand" "T,U,G,ro,rG"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T, r, o")
+ (match_operand:DF 1 "input_operand" " T,U,G,ro,rG"))]
"! TARGET_FPU
&& TARGET_V9
&& ! TARGET_ARCH64
@@ -2027,8 +2027,8 @@ (define_insn "*movdf_insn_sp32_v9_no_fpu
;; We have available both v9 double floats and 64-bit integer registers.
(define_insn "*movdf_insn_sp64"
- [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r")
- (match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY,m,*rGY,DF"))]
+ [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e, e,W, *r,*r, m,*r")
+ (match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY, m,*rGY,FD"))]
"TARGET_FPU
&& TARGET_ARCH64
&& (register_operand (operands[0], <V64:MODE>mode)
@@ -2047,8 +2047,8 @@ (define_insn "*movdf_insn_sp64"
(set_attr "fptype" "double,double,*,*,*,*,*,*")])
(define_insn "*movdf_insn_sp64_no_fpu"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
- (match_operand:DF 1 "input_operand" "r,m,rG"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r, m")
+ (match_operand:DF 1 "input_operand" "r,m,rG"))]
"! TARGET_FPU
&& TARGET_ARCH64
&& (register_operand (operands[0], DFmode)
@@ -2288,8 +2288,8 @@ (define_expand "movtf"
})
(define_insn "*movtf_insn_sp32"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,U,r")
- (match_operand:TF 1 "input_operand" "G,oe,GeUr,o,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o,U, r")
+ (match_operand:TF 1 "input_operand" " G,oe,GeUr,o,roG"))]
"TARGET_FPU
&& ! TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
@@ -2302,8 +2302,8 @@ (define_insn "*movtf_insn_sp32"
;; when -mno-fpu.
(define_insn "*movtf_insn_sp32_no_fpu"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
- (match_operand:TF 1 "input_operand" "G,o,U,roG,r"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o, r,o")
+ (match_operand:TF 1 "input_operand" " G,o,U,roG,r"))]
"! TARGET_FPU
&& ! TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
@@ -2312,8 +2312,8 @@ (define_insn "*movtf_insn_sp32_no_fpu"
[(set_attr "length" "4")])
(define_insn "*movtf_insn_sp64"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,r")
- (match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o, r")
+ (match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
"TARGET_FPU
&& TARGET_ARCH64
&& ! TARGET_HARD_QUAD
@@ -2323,8 +2323,8 @@ (define_insn "*movtf_insn_sp64"
[(set_attr "length" "2")])
(define_insn "*movtf_insn_sp64_hq"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m,o,r")
- (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m, o, r")
+ (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
"TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
@@ -2341,8 +2341,8 @@ (define_insn "*movtf_insn_sp64_hq"
(set_attr "length" "2,*,*,*,2,2")])
(define_insn "*movtf_insn_sp64_no_fpu"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
- (match_operand:TF 1 "input_operand" "orG,rG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "= r, o")
+ (match_operand:TF 1 "input_operand" "orG,rG"))]
"! TARGET_FPU
&& TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
