Hello!
This pattern is not needed because all x87 float_extend RTXes
degenerate to a plain
move (or a no-op move).
2018-09-11 Uros Bizjak <ubiz...@gmail.com>
* config/i386/i386.md (sqrt_extend<mode>xf3_i387): Remove.
(sqrt<mode>2): Extend operand 1 to XFmode and generate sqrtxf3 insn.
Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 264242)
+++ config/i386/i386.md (working copy)
@@ -15126,19 +15126,6 @@
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "direct")])
-(define_insn "sqrt_extend<mode>xf2_i387"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (sqrt:XF
- (float_extend:XF
- (match_operand:MODEF 1 "register_operand" "0"))))]
- "TARGET_USE_FANCY_MATH_387"
- "fsqrt"
- [(set_attr "type" "fpspc")
- (set_attr "mode" "XF")
- (set_attr "athlon_decode" "direct")
- (set_attr "amdfam10_decode" "direct")
- (set_attr "bdver1_decode" "direct")])
-
(define_insn "*rsqrtsf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x,x")
(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
@@ -15201,9 +15188,10 @@
if (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
{
rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = force_reg (<MODE>mode, operands[1]);
+ rtx op1 = gen_reg_rtx (XFmode);
- emit_insn (gen_sqrt_extend<mode>xf2_i387 (op0, op1));
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_sqrtxf2 (op0, op1));
emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
DONE;
}
