On Fri, May 4, 2018 at 5:21 PM, Bin Cheng <bin.ch...@arm.com> wrote: > Hi, > This is the updated version patch set computing register pressure on TREE SSA > and use that information to direct other loop optimizers (predcom only for > now). > This version of change is to follow Jeff's comment that we should reuse > existing > tree-ssa-live.c infrastructure for live range computation, rather than > inventing > another one. > Jeff had another concern about exposing ira.h and low-level register stuff in > GIMPLE world. Unfortunately I haven't got a clear solution to it. I found > it's > a bit hard to relate type/type_mode with register class and with available > regs > without exposing the information, especially there are multiple possible > register > classes for vector types and it's not fixed. I am open to any suggestions > here. > > This is the first patch estimating the map from type mode to register class. > This one doesn't need update and it's the same as the original version patch > at https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01021.html > > Bootstrap and test on x86_64 and AArch64 ongoing. Any comments? Hi, The original version of this patch was approved by Jeff @https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01808.html Jeff, some new comment now or the old approval is still valid? Guess your major concern is about exporting ira.h to gimple world?
Thanks, bin > > Thanks, > bin > 2018-04-27 Bin Cheng <bin.ch...@arm.com> > > * ira.c (setup_mode_classes): New function. > (find_reg_classes): Call above function. > * ira.h (struct target_ira): New field x_ira_mode_classes. > (ira_mode_classes): New macro.
