Hi,
This is the updated version patch set computing register pressure on TREE SSA
and use that information to direct other loop optimizers (predcom only for now).
This version of change is to follow Jeff's comment that we should reuse existing
tree-ssa-live.c infrastructure for live range computation, rather than inventing
another one.
Jeff had another concern about exposing ira.h and low-level register stuff in
GIMPLE world. Unfortunately I haven't got a clear solution to it. I found it's
a bit hard to relate type/type_mode with register class and with available regs
without exposing the information, especially there are multiple possible
register
classes for vector types and it's not fixed. I am open to any suggestions here.
This is the first patch estimating the map from type mode to register class.
This one doesn't need update and it's the same as the original version patch
at https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01021.html
Bootstrap and test on x86_64 and AArch64 ongoing. Any comments?
Thanks,
bin
2018-04-27 Bin Cheng <bin.ch...@arm.com>
* ira.c (setup_mode_classes): New function.
(find_reg_classes): Call above function.
* ira.h (struct target_ira): New field x_ira_mode_classes.
(ira_mode_classes): New macro.From d65c160a37f785cff29172f1335e87d01fc260ba Mon Sep 17 00:00:00 2001
From: Bin Cheng <binch...@e108451-lin.cambridge.arm.com>
Date: Mon, 24 Apr 2017 14:41:28 +0100
Subject: [PATCH 1/6] ira-mode-reg_class-map-20170316.txt
---
gcc/ira.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
gcc/ira.h | 7 ++++++
2 files changed, 84 insertions(+)
diff --git a/gcc/ira.c b/gcc/ira.c
index b7bcc15..f132a7a 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -1154,6 +1154,82 @@ setup_class_translate (void)
ira_pressure_classes_num, ira_pressure_classes);
}
+/* Find desired register class for machine mode from information about
+ register pressure class. On RTL level, we can compute preferred
+ register class infomation for each pseudo register or allocno. On
+ GIMPLE level, we need to infer register class from variable's type,
+ i.e, we need map from type mode to register class.
+
+ The map information is computed by simple guess, it's good enough
+ for use on GIMPLE. */
+void
+setup_mode_classes (void)
+{
+ int i, j;
+ machine_mode mode;
+ enum reg_class vector_class = NO_REGS;
+
+ for (i = 0; i < NUM_MACHINE_MODES; i++)
+ {
+ mode = (machine_mode) i;
+ ira_mode_classes[mode] = NO_REGS;
+
+ /* Only care about integer, float and vector modes on GIMPLE. */
+ if (!INTEGRAL_MODE_P (mode)
+ && !FLOAT_MODE_P (mode) && !VECTOR_MODE_P (mode))
+ continue;
+
+ /* Integers must be in GENERAL_REGS by default. */
+ if (SCALAR_INT_MODE_P (mode))
+ {
+ ira_mode_classes[mode] = GENERAL_REGS;
+ continue;
+ }
+
+ /* Iterate over pressure classes and find the most appropriate
+ one for this mode. */
+ for (j = 0; j < ira_pressure_classes_num; j++)
+ {
+ HARD_REG_SET valid_for_cl;
+ enum reg_class cl = ira_pressure_classes[j];
+
+ if (!contains_reg_of_mode[cl][mode])
+ continue;
+
+ COPY_HARD_REG_SET (valid_for_cl, reg_class_contents[cl]);
+ AND_COMPL_HARD_REG_SET (valid_for_cl,
+ ira_prohibited_class_mode_regs[cl][mode]);
+ AND_COMPL_HARD_REG_SET (valid_for_cl, ira_no_alloc_regs);
+ if (hard_reg_set_empty_p (valid_for_cl))
+ continue;
+
+ if (ira_mode_classes[mode] == NO_REGS)
+ {
+ ira_mode_classes[mode] = cl;
+
+ /* Record reg_class for vector mode. */
+ if (VECTOR_MODE_P (mode) && cl != NO_REGS)
+ vector_class = cl;
+
+ continue;
+ }
+ /* Prefer non GENERAL_REGS for floating points. */
+ if ((FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
+ && cl != GENERAL_REGS && ira_mode_classes[mode] == GENERAL_REGS)
+ ira_mode_classes[mode] = cl;
+ }
+ }
+
+ /* Setup vector modes that are missed previously. */
+ if (vector_class != NO_REGS)
+ for (i = 0; i < NUM_MACHINE_MODES; i++)
+ {
+ mode = (machine_mode) i;
+ if (ira_mode_classes[mode] == NO_REGS && VECTOR_MODE_P (mode))
+ ira_mode_classes[mode] = vector_class;
+ }
+}
+
/* Order numbers of allocno classes in original target allocno class
array, -1 for non-allocno classes. */
static int allocno_class_order[N_REG_CLASSES];
@@ -1430,6 +1506,7 @@ find_reg_classes (void)
setup_class_translate ();
reorder_important_classes ();
setup_reg_class_relations ();
+ setup_mode_classes ();
}
diff --git a/gcc/ira.h b/gcc/ira.h
index 9df983c..3471d4c 100644
--- a/gcc/ira.h
+++ b/gcc/ira.h
@@ -66,6 +66,11 @@ struct target_ira
class. */
enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
+ /* Map of machine mode to register pressure class. With this map,
+ coarse-grained register pressure can be computed on GIMPLE, where
+ we don't have insn pattern to compute preferred reg class. */
+ enum reg_class x_ira_mode_classes[MAX_MACHINE_MODE];
+
/* Biggest pressure register class containing stack registers.
NO_REGS if there are no stack registers. */
enum reg_class x_ira_stack_reg_pressure_class;
@@ -140,6 +145,8 @@ extern struct target_ira *this_target_ira;
(this_target_ira->x_ira_pressure_classes)
#define ira_pressure_class_translate \
(this_target_ira->x_ira_pressure_class_translate)
+#define ira_mode_classes \
+ (this_target_ira->x_ira_mode_classes)
#define ira_stack_reg_pressure_class \
(this_target_ira->x_ira_stack_reg_pressure_class)
#define ira_reg_class_max_nregs \
--
1.9.1
