On Mon, Jan 22, 2018 at 12:32:13PM -0600, Segher Boessenkool wrote: > Hi Mike, > > Thanks for doing this! > > On Sun, Jan 21, 2018 at 07:03:58PM -0500, Michael Meissner wrote: > > With these patches, the generator code issues an UNSPEC (signbit<mode>2_dm) > > just to get the high double word, and the shift right is then emitted. The > > UNSPEC only handles the value being in either vector or GPR register. > > There is > > a second UNSPEC that is created by the combiner if the value is in memory. > > On > > little endian systems, the first split pass (before register allocation) > > will > > allocate a pseudo register to hold the initial ADD of the base and index > > registers for indexed loads, and then forms a LD reg,8(tmp) to load the high > > word. Just in case, some code after register allocation reforms the > > UNSPEC, it > > uses a base register for the load, and it can use the base register as > > needed > > for the temporary. > > But does it have to do an unspec at all? Can't it just immediately take > the relevant 64-bit half (during expand), no unspec in sight, and that > is that?
Yes it needs the UNSPEC. As I said, you can't use SUBREG due to a combination of MODES_TIEABLE_P and the way things are represented in vector registers (with the scalar part being in the upper part of the register). I tried it, and could not get it to work. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
