On Tue, Jan 16, 2018 at 10:55:43PM -0500, Michael Meissner wrote: > PR target/83862 pointed out a problem I put into the 128-bit floating point > type signbit optimization. The issue is we want to avoid doing a load to a > floating point/vector register and then a direct move to do signbit, so we > change the load to load the upper 64-bits of the floating point value to get > the sign bit. Unfortunately, if the type is IEEE 128-bit and memory is > addressed with an indexed address on a little endian system, it generates an > illegal address and generates an internal compiler error.
So all this is caused by these splitters running after reload. Why do we have to do that? Do we? We should be able to just change it to a subreg and shift, early already? Segher
