On 18/10/11 13:47, Bernd Schmidt wrote: > On 10/18/11 14:30, Richard Earnshaw wrote: >> Well, if that's the case why do we need to test for Thumb1 at all? And >> why do we only enable write-back for Thumb1? other ISA variants can >> also do that (I know that Thumb1 requires write-back, but it's >> optionally available for the other ISA flavours). > > We're not trying to generate a writeback sequence with our peepholes. > The problem is that on Thumb, that's the only instruction available, and > we want to make use of it if possible (i.e. register dead afterwards etc.). > > > Bernd >
OK, I understand now. However, I think it's misleading to talk about thumb1 directly here -- it implies that this doesn't apply in other cases. A better patch, would be (I think) --- gcc/config/arm/arm.c (revision 175906) +++ gcc/config/arm/arm.c (working copy) @@ -9950,7 +9950,9 @@ store_multiple_sequence (rtx *operands, /* If it isn't an integer register, then we can't do this. */ if (unsorted_regs[i] < 0 || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) - || (TARGET_THUMB2 && unsorted_regs[i] == base_reg) + /* The effects are unpredictable if the base reg is + both updated and stored. */ + || (base_writeback && unsorted_regs[i] == base_reg) || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM) || unsorted_regs[i] > 14) return 0; and then initialize base_writeback at the entry to the function (I presume that currently we would just set it to be TARGET_THUMB1), perhaps with a comment saying that we don't currently support base_writeback for other ISA variants. R.