On 18/10/11 13:19, Bernd Schmidt wrote: > On 10/17/11 14:54, Richard Earnshaw wrote: >> On 14/10/11 14:31, Bernd Schmidt wrote: >>> On 07/13/11 16:03, Richard Earnshaw wrote: >>>>> * config/arm/arm.c (store_multiple_sequence): Avoid cases where >>>>> the base reg is stored iff compiling for Thumb1. >>>>> >>>>> * gcc.target/arm/pr49641.c: New test. >>> >>> Ping. Richard, you replied to the mail but didn't comment on the patch. >>> >>> >>> Bernd >>> >> >> >> Sorry, I thought I'd made it clear that I don't think the compiler >> should ever use STM with write-back if the base register is in the >> stored list. We must certainly never do it if the base register is not >> the first register in the list as this has always been unpredictable. >> >> BTW, this is not Thumb1 specific, it applies at all times. >> >> >> So, no the patch is not OK as it stands. > > I'm confused. The patch disables the STM if THUMB1 and the base register > is in the stored list. We only ever enable write-back for Thumb1 (see > gen_stm_seq). So, what's the problem?
Well, if that's the case why do we need to test for Thumb1 at all? And why do we only enable write-back for Thumb1? other ISA variants can also do that (I know that Thumb1 requires write-back, but it's optionally available for the other ISA flavours). R.
