This patch passes the number of units to aarch64_expand_vec_perm
and aarch64_expand_vec_perm_const, which avoids a to_constant ()
once GET_MODE_NUNITS is variable.
2017-10-27 Richard Sandiford <richard.sandif...@linaro.org>
Alan Hayward <alan.hayw...@arm.com>
David Sherwood <david.sherw...@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_expand_vec_perm)
(aarch64_expand_vec_perm_const): Take the number of units too.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm)
(aarch64_expand_vec_perm_const): Likewise.
* config/aarch64/aarch64-simd.md (vec_perm_const<mode>)
(vec_perm<mode>): Update accordingly.
Index: gcc/config/aarch64/aarch64-protos.h
===================================================================
--- gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:07.203885483 +0100
+++ gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:11.042239887 +0100
@@ -484,11 +484,11 @@ tree aarch64_builtin_rsqrt (unsigned int
tree aarch64_builtin_vectorized_function (unsigned int, tree, tree);
extern void aarch64_split_combinev16qi (rtx operands[3]);
-extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
+extern void aarch64_expand_vec_perm (rtx, rtx, rtx, rtx, unsigned int);
extern bool aarch64_madd_needs_nop (rtx_insn *);
extern void aarch64_final_prescan_insn (rtx_insn *);
extern bool
-aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
+aarch64_expand_vec_perm_const (rtx, rtx, rtx, rtx, unsigned int);
void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
int aarch64_ccmp_mode_to_code (machine_mode mode);
Index: gcc/config/aarch64/aarch64.c
===================================================================
--- gcc/config/aarch64/aarch64.c 2017-10-27 14:12:07.205742901 +0100
+++ gcc/config/aarch64/aarch64.c 2017-10-27 14:12:11.045026014 +0100
@@ -13488,11 +13488,14 @@ aarch64_expand_vec_perm_1 (rtx target, r
}
}
+/* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
+ NELT is the number of elements in the vector. */
+
void
-aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
+aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel,
+ unsigned int nelt)
{
machine_mode vmode = GET_MODE (target);
- unsigned int nelt = GET_MODE_NUNITS (vmode);
bool one_vector_p = rtx_equal_p (op0, op1);
rtx mask;
@@ -13848,13 +13851,15 @@ aarch64_expand_vec_perm_const_1 (struct
return false;
}
-/* Expand a vec_perm_const pattern. */
+/* Expand a vec_perm_const pattern with the operands given by TARGET,
+ OP0, OP1 and SEL. NELT is the number of elements in the vector. */
bool
-aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel)
+aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel,
+ unsigned int nelt)
{
struct expand_vec_perm_d d;
- int i, nelt, which;
+ unsigned int i, which;
d.target = target;
d.op0 = op0;
@@ -13864,12 +13869,11 @@ aarch64_expand_vec_perm_const (rtx targe
gcc_assert (VECTOR_MODE_P (d.vmode));
d.testing_p = false;
- nelt = GET_MODE_NUNITS (d.vmode);
d.perm.reserve (nelt);
for (i = which = 0; i < nelt; ++i)
{
rtx e = XVECEXP (sel, 0, i);
- int ei = INTVAL (e) & (2 * nelt - 1);
+ unsigned int ei = INTVAL (e) & (2 * nelt - 1);
which |= (ei < nelt ? 1 : 2);
d.perm.quick_push (ei);
}
Index: gcc/config/aarch64/aarch64-simd.md
===================================================================
--- gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:07.203885483 +0100
+++ gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:11.043168596 +0100
@@ -5238,7 +5238,7 @@ (define_expand "vec_perm_const<mode>"
"TARGET_SIMD"
{
if (aarch64_expand_vec_perm_const (operands[0], operands[1],
- operands[2], operands[3]))
+ operands[2], operands[3], <nunits>))
DONE;
else
FAIL;
@@ -5252,7 +5252,7 @@ (define_expand "vec_perm<mode>"
"TARGET_SIMD"
{
aarch64_expand_vec_perm (operands[0], operands[1],
- operands[2], operands[3]);
+ operands[2], operands[3], <nunits>);
DONE;
})
