Bernd Schmidt <ber...@codesourcery.com> writes:
> @@ -10227,17 +10236,30 @@ mips_expand_prologue (void)
>      emit_insn (gen_blockage ());
>  }
>  
> -/* Emit instructions to restore register REG from slot MEM.  */
> +/* Emit instructions to restore register REG from slot MEM.  Also update
> +   the cfa_restores list.  */
>  
>  static void
>  mips_restore_reg (rtx reg, rtx mem)
>  {
> +  rtx orig_reg = reg;
> +  rtx last;
> +
>    /* There's no MIPS16 instruction to load $31 directly.  Load into
>       $7 instead and adjust the return insn appropriately.  */
>    if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
>      reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
>  
>    mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
> +  if (reg == orig_reg)
> +    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
> +
> +  if (!frame_pointer_needed || REGNO (reg) != HARD_FRAME_POINTER_REGNUM)
> +    return;
> +  last = get_last_insn ();
> +  add_reg_note (last, REG_CFA_DEF_CFA, plus_constant (stack_pointer_rtx,
> +                                                   cfa_sp_offset));
> +  RTX_FRAME_RELATED_P (last) = 1;

I suppose I still don't get why this is OK but this:

> @@ -10324,12 +10350,26 @@ mips_expand_epilogue (bool sibcall_p)
>        if (!TARGET_MIPS16)
>       target = stack_pointer_rtx;
>  
> -      emit_insn (gen_add3_insn (target, base, adjust));
> +      insn = emit_insn (gen_add3_insn (target, base, adjust));
> +      if (!frame_pointer_needed && target == stack_pointer_rtx)
> +     {
> +       RTX_FRAME_RELATED_P (insn) = 1;
> +       add_reg_note (insn, REG_CFA_DEF_CFA,
> +                     plus_constant (stack_pointer_rtx, step2));
> +     }

triggered ICEs without the !frame_pointer_required.  I think I need
to play around with it a bit before I understand enough to review.
I'll try to find time this weekend.

Also, this:

@@ -10442,7 +10495,7 @@ mips_expand_epilogue (bool sibcall_p)
        }
       else
        {
-         unsigned int regno;
+         rtx pat;
 
          /* When generating MIPS16 code, the normal
             mips_for_each_saved_gpr_and_fpr path will restore the return
@@ -10450,11 +10503,16 @@ mips_expand_epilogue (bool sibcall_p)
          if (TARGET_MIPS16
              && !GENERATE_MIPS16E_SAVE_RESTORE
              && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
-           regno = GP_REG_FIRST + 7;
+           {
+             rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
+             pat = gen_return_internal (reg);
+           }
          else
-           regno = RETURN_ADDR_REGNUM;
-         emit_jump_insn (gen_simple_return_internal (gen_rtx_REG (Pmode,
-                                                                  regno)));
+           {
+             rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
+             pat = gen_simple_return_internal (reg);
+           }
+         emit_jump_insn (pat);
        }
     }
 
looks like a logically separate change.  I'm not sure I understand
why it's needed: both returns are simple returns in the rtx sense.

Sorry for being awkward here :-(

Richard

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