Hi, I've prepared a new patch based on the received review (attached). I also added a mod on invoke.texi regarding mll64 documentation. This mod was missing in the first patch.
I have tested it with dg.exp for arc700, archs and archs+ll64.
Please let me know if everything is alright.
Thank you,
Claudiu
gcc/
2015-01-19 Claudiu Zissulescu <claz...@synopsys.com>
* config/arc/arc.c (TARGET_DWARF_REGISTER_SPAN): Define.
(arc_init): Check validity mll64 option.
(arc_save_restore): Use double load/store instruction.
(arc_expand_movmem): Likewise.
(arc_split_move): Don't split if we have double load/store
instructions. Returns a boolean.
(arc_process_double_reg_moves): Change function to return boolean
instead of a sequence of instructions.
(arc_dwarf_register_span): New function.
* config/arc/arc-protos.h (arc_split_move): Change prototype.
* config/arc/arc.h (TARGET_CPU_CPP_BUILTINS): Define __ARC_LL64__.
* config/arc/arc.md (*movdi_insn): Emit ldd/std instructions.
(*movdf_insn): Likewise.
* config/arc/arc.opt (mll64): New option.
* config/arc/predicates.md (even_register_operand): New predicate.
* doc/invoke.texi (ARC Options): Add mll64 documentation
> -----Original Message-----
> From: Joern Wolfgang Rennecke [mailto:g...@amylaar.uk]
> Sent: Sunday, January 17, 2016 7:21 AM
> To: Claudiu Zissulescu; gcc-patches@gcc.gnu.org
> Cc: Francois Bedard; jeremy.benn...@embecosm.com
> Subject: Re: [PATCH] [ARC] Add basic support for double load and store
> instructions
>
>
>
> On 15/01/16 12:40, Claudiu Zissulescu wrote:
>
> (arc_save_restore): Use double load/store instruction.
> (arc_expand_movmem): Likewise.
>
>
> > if (n_pieces >= (unsigned int) (optimize_size ? 3 : 15))
> > return false;
> > - if (piece > 4)
> > + if (TARGET_LL64 && (piece != 8) && (align >= 4))
> > + piece = 8;
> > + else if (piece > 4)
> > piece = 4;
> > dst_addr = force_offsettable (XEXP (operands[0], 0), size, 0);
>
> That bit doesn't make sense to me.
> Assume the alignment is 8. Thus, piece becomes 8 too. Then the above
> conditional gets processed, and it sets piece to 4.
> I think instead of "(piece != 8) && (align >= 4)" it should be:
> "(piece >= 8)"
>
> * config/arc/arc.md (*movdi_insn): Emit ldd/std instructions.
>
>
> > - "&& reload_completed && optimize"
> > - [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5))]
> > - "arc_split_move (operands);"
> > + "reload_completed"
> > + [(match_dup 2)]
> > + "operands[2] = arc_split_move (operands);"
>
> arc_split_move uses, inter alia, operands[2]..operands[[5].
> Thus, it is not save to stop mentioning these in the pattern.
>
> > (*movdf_insn): Likewise.
> Likewise.
>
> When you say 'basic support', I suppose you have a plan to re-visit this later
> to get the register allocator to use register pairs, and stop regrename
> breaking them up?
0001-ARC-Add-basic-support-for-double-load-and-store-inst.patch
Description: 0001-ARC-Add-basic-support-for-double-load-and-store-inst.patch
