> > if (n_pieces >= (unsigned int) (optimize_size ? 3 : 15)) > > return false; > > - if (piece > 4) > > + if (TARGET_LL64 && (piece != 8) && (align >= 4)) > > + piece = 8; > > + else if (piece > 4) > > piece = 4; > > dst_addr = force_offsettable (XEXP (operands[0], 0), size, 0); > > That bit doesn't make sense to me. > Assume the alignment is 8. Thus, piece becomes 8 too. Then the above > conditional gets processed, and it sets piece to 4. > I think instead of "(piece != 8) && (align >= 4)" it should be: > "(piece >= 8)"
Right. My intention is to force 64 bit transfer also for 32 bit datum. Hence, the condition should be like this: If (TARGET_LL64 && (piece >= 4)) piece = 8; ... So, whenever the align is 32 bit or larger (as piece is align), we use the 64 bit transfers. The number of pieces is computed few lines above. > > * config/arc/arc.md (*movdi_insn): Emit ldd/std instructions. > > > > - "&& reload_completed && optimize" > > - [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5))] > > - "arc_split_move (operands);" > > + "reload_completed" > > + [(match_dup 2)] > > + "operands[2] = arc_split_move (operands);" > > arc_split_move uses, inter alia, operands[2]..operands[[5]. > Thus, it is not save to stop mentioning these in the pattern. > > > (*movdf_insn): Likewise. > Likewise. > Noted. > When you say 'basic support', I suppose you have a plan to re-visit this later > to get the register allocator to use register pairs, and stop regrename > breaking them up? Indeed, I am preparing a patch for (new) floating point support which I am very interested to get ur feedback. The double precision floating point operations are using the double registers. Hence, breaking the registers and, afterwards, introducing moves to get them right, it is not desirable. Thus, I will introduce a new abi variant which will pass the arguments on even-odd registers and mods in the hard_regno_mode_ok to keep the registers in proper pairs. But more in the upcoming patch.
