On 11/04/2015 02:39 AM, Dominik Vogt wrote: > On Tue, Nov 03, 2015 at 06:47:28PM +0100, Ulrich Weigand wrote: >> Dominik Vogt wrote: >> >>> @@ -2936,7 +2936,7 @@ >>> (set (mem:BLK (match_operand:P 1 "register_operand" "0")) >>> (mem:BLK (match_operand:P 3 "register_operand" "2"))) >>> (set (match_operand:P 0 "register_operand" "=d") >>> - (unspec [(mem:BLK (match_dup 1)) >>> + (unspec:P [(mem:BLK (match_dup 1)) >>> (mem:BLK (match_dup 3)) >>> (reg:SI 0)] UNSPEC_MVST)) >>> (clobber (reg:CC CC_REGNUM))] >> >> Don't you have to change the expander too? Otherwise the >> pattern will no longer match ... > > Yes, you're right. This turned out to be a bit tricky to do > because the "movstr" expander doesn't allow variants with > different modes. :-/ > > New patch attached, including a test case that works on 31-bit and > 64-bit.
Could you please check that the generated code doesn't change with a larger code base (e.g. speccpu)? It should not affect it but I really think we omitted the mode here for a reason (although I don't remember why). -Andreas-
