Hello Uroš,
I've merged two patches together and rebased it
on top of gcc-5-branch. The only change I made compared
to trunk version is scheduling set to CPU_NEHALEM since
CPU_HASWELL is not supported in gcc-5.
Bootstrapped.
Is it ok for gcc-5-branch?
gcc/
* config.gcc: Support "skylake-avx512".
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
PROCESSOR_SKYLAKE_AVX512.
* config/i386/i386.c (m_SKYLAKE_AVX512): Define.
(processor_target_table): Add "skylake-avx512".
(PTA_SKYLAKE): Define.
(ix86_option_override_internal): Add "skylake-avx512".
(fold_builtin_cpu): Handle "skylake-avx512".
* config/i386/i386.h (TARGET_SKYLAKE_AVX512): Define.
(processor_type): Add PROCESSOR_SKYLAKE_AVX512.
* doc/invoke.texi (skylake-avx512): New.
libgcc/
* libgcc/config/i386/cpuinfo.c (get_intel_cpu): Detect "skylake-avx512",
AES, PCLMUL, AVX-512VL, AVX-512BW, AVX-512DQ, AVX-512PF,
AVX-512ER, AVX-512CD.
gcc/testsuite/
* gcc.target/i386/builtin_target.c: Add check for "skylake-avx512",
"aes"
and "pclmul".
* gcc.target/i386/funcspec-5.c: Test avx512vl, avx512bw,
avx512dq, avx512cd, avx512er, avx512pf and skylake-avx512.
--
Thanks, K
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c835734..207fc65 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -589,8 +589,8 @@ pentium4 pentium4m pentiumpro prescott"
x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
bdver3 bdver4 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
-sandybridge ivybridge haswell broadwell bonnell silvermont knl x86-64 \
-native"
+sandybridge ivybridge haswell broadwell bonnell silvermont knl \
+skylake-avx512 x86-64 native"
# Additional x86 processors supported by --with-cpu=. Each processor
# MUST be separated by exactly one space.
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index f3f90df..4f20e14 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -185,6 +185,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__knl");
def_or_undef (parse_in, "__knl__");
break;
+ case PROCESSOR_SKYLAKE_AVX512:
+ def_or_undef (parse_in, "__skylake_avx512");
+ def_or_undef (parse_in, "__skylake_avx512__");
+ break;
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
break;
@@ -294,6 +298,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_KNL:
def_or_undef (parse_in, "__tune_knl__");
break;
+ case PROCESSOR_SKYLAKE_AVX512:
+ def_or_undef (parse_in, "__tune_skylake_avx512__");
+ break;
case PROCESSOR_INTEL:
case PROCESSOR_GENERIC:
break;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 9b17256..43e6f91 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2054,6 +2054,7 @@ const struct processor_costs *ix86_cost = &pentium_cost;
#define m_BONNELL (1<<PROCESSOR_BONNELL)
#define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
#define m_KNL (1<<PROCESSOR_KNL)
+#define m_SKYLAKE_AVX512 (1<<PROCESSOT_SKYLAKE_AVX512)
#define m_INTEL (1<<PROCESSOR_INTEL)
#define m_GEODE (1<<PROCESSOR_GEODE)
@@ -2522,6 +2523,7 @@ static const struct ptt
processor_target_table[PROCESSOR_max] =
{"bonnell", &atom_cost, 16, 15, 16, 7, 16},
{"silvermont", &slm_cost, 16, 15, 16, 7, 16},
{"knl", &slm_cost, 16, 15, 16, 7, 16},
+ {"skylake-avx512", &core_cost, 16, 10, 16, 10, 16},
{"intel", &intel_cost, 16, 15, 16, 7, 16},
{"geode", &geode_cost, 0, 0, 0, 0, 0},
{"k6", &k6_cost, 32, 7, 32, 7, 32},
@@ -3210,6 +3212,10 @@ ix86_option_override_internal (bool main_args_p,
| PTA_FMA | PTA_MOVBE | PTA_HLE)
#define PTA_BROADWELL \
(PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
+#define PTA_SKYLAKE_AVX512 \
+ (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES \
+ | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \
+ | PTA_AVX512BW | PTA_AVX512DQ)
#define PTA_KNL \
(PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
#define PTA_BONNELL \
@@ -3271,6 +3277,7 @@ ix86_option_override_internal (bool main_args_p,
{"haswell", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_HASWELL},
{"core-avx2", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_HASWELL},
{"broadwell", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_BROADWELL},
+ {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_NEHALEM,
PTA_SKYLAKE_AVX512},
{"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
{"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
{"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
@@ -35556,6 +35563,14 @@ fold_builtin_cpu (tree fndecl, tree *args)
F_AVX512F,
F_BMI,
F_BMI2,
+ F_AES,
+ F_PCLMUL,
+ F_AVX512VL,
+ F_AVX512BW,
+ F_AVX512DQ,
+ F_AVX512CD,
+ F_AVX512ER,
+ F_AVX512PF,
F_MAX
};
@@ -35589,7 +35604,9 @@ fold_builtin_cpu (tree fndecl, tree *args)
M_AMDFAM15H_BDVER4,
M_INTEL_COREI7_IVYBRIDGE,
M_INTEL_COREI7_HASWELL,
- M_INTEL_COREI7_BROADWELL
+ M_INTEL_COREI7_BROADWELL,
+ M_INTEL_COREI7_SKYLAKE,
+ M_INTEL_COREI7_SKYLAKE_AVX512
};
static struct _arch_names_table
@@ -35611,6 +35628,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
{"ivybridge", M_INTEL_COREI7_IVYBRIDGE},
{"haswell", M_INTEL_COREI7_HASWELL},
{"broadwell", M_INTEL_COREI7_BROADWELL},
+ {"skylake", M_INTEL_COREI7_SKYLAKE},
+ {"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512},
{"bonnell", M_INTEL_BONNELL},
{"silvermont", M_INTEL_SILVERMONT},
{"knl", M_INTEL_KNL},
@@ -35634,24 +35653,32 @@ fold_builtin_cpu (tree fndecl, tree *args)
}
const isa_names_table[] =
{
- {"cmov", F_CMOV},
- {"mmx", F_MMX},
- {"popcnt", F_POPCNT},
- {"sse", F_SSE},
- {"sse2", F_SSE2},
- {"sse3", F_SSE3},
- {"ssse3", F_SSSE3},
- {"sse4a", F_SSE4_A},
- {"sse4.1", F_SSE4_1},
- {"sse4.2", F_SSE4_2},
- {"avx", F_AVX},
- {"fma4", F_FMA4},
- {"xop", F_XOP},
- {"fma", F_FMA},
- {"avx2", F_AVX2},
- {"avx512f",F_AVX512F},
- {"bmi", F_BMI},
- {"bmi2", F_BMI2}
+ {"cmov", F_CMOV},
+ {"mmx", F_MMX},
+ {"popcnt", F_POPCNT},
+ {"sse", F_SSE},
+ {"sse2", F_SSE2},
+ {"sse3", F_SSE3},
+ {"ssse3", F_SSSE3},
+ {"sse4a", F_SSE4_A},
+ {"sse4.1", F_SSE4_1},
+ {"sse4.2", F_SSE4_2},
+ {"avx", F_AVX},
+ {"fma4", F_FMA4},
+ {"xop", F_XOP},
+ {"fma", F_FMA},
+ {"avx2", F_AVX2},
+ {"avx512f", F_AVX512F},
+ {"bmi", F_BMI},
+ {"bmi2", F_BMI2},
+ {"aes", F_AES},
+ {"pclmul", F_PCLMUL},
+ {"avx512vl",F_AVX512VL},
+ {"avx512bw",F_AVX512BW},
+ {"avx512dq",F_AVX512DQ},
+ {"avx512cd",F_AVX512CD},
+ {"avx512er",F_AVX512ER},
+ {"avx512pf",F_AVX512PF},
};
tree __processor_model_type = build_processor_model_struct ();
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index de43f06..f913348 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -340,6 +340,7 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
#define TARGET_KNL (ix86_tune == PROCESSOR_KNL)
+#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2278,6 +2279,7 @@ enum processor_type
PROCESSOR_BONNELL,
PROCESSOR_SILVERMONT,
PROCESSOR_KNL,
+ PROCESSOR_SKYLAKE_AVX512,
PROCESSOR_INTEL,
PROCESSOR_GEODE,
PROCESSOR_K6,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d3be589..99a9027 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22060,6 +22060,12 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL,
FSGSBASE, RDRND, FMA,
BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER and
AVX512CD instruction set support.
+@item skylake-avx512
+Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
+AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
+
@item k6
AMD K6 CPU with MMX instruction set support.
diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c
b/gcc/testsuite/gcc.target/i386/builtin_target.c
index 10c0568..591d1c7 100644
--- a/gcc/testsuite/gcc.target/i386/builtin_target.c
+++ b/gcc/testsuite/gcc.target/i386/builtin_target.c
@@ -80,6 +80,11 @@ check_intel_cpu_model (unsigned int family, unsigned int
model,
assert (__builtin_cpu_is ("corei7"));
assert (__builtin_cpu_is ("broadwell"));
break;
+ case 0x55:
+ /* Skylake with AVX-512 support. */
+ assert (__builtin_cpu_is ("corei7"));
+ assert (__builtin_cpu_is ("skylake-avx512"));
+ break;
case 0x17:
case 0x1d:
/* Penryn. */
@@ -177,6 +182,18 @@ check_features (unsigned int ecx, unsigned int edx,
assert (__builtin_cpu_supports ("avx2"));
if (ebx & bit_AVX512F)
assert (__builtin_cpu_supports ("avx512f"));
+ if (ebx & bit_AVX512VL)
+ assert (__builtin_cpu_supports ("avx512vl"));
+ if (ebx & bit_AVX512CD)
+ assert (__builtin_cpu_supports ("avx512cd"));
+ if (ebx & bit_AVX512PF)
+ assert (__builtin_cpu_supports ("avx512pf"));
+ if (ebx & bit_AVX512ER)
+ assert (__builtin_cpu_supports ("avx512er"));
+ if (ebx & bit_AVX512BW)
+ assert (__builtin_cpu_supports ("avx512bw"));
+ if (ebx & bit_AVX512DQ)
+ assert (__builtin_cpu_supports ("avx512dq"));
}
}
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-5.c
b/gcc/testsuite/gcc.target/i386/funcspec-5.c
index 7185b5c..c43bc76 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-5.c
+++ b/gcc/testsuite/gcc.target/i386/funcspec-5.c
@@ -25,6 +25,12 @@ extern void test_tbm (void)
__attribute__((__target__("tbm")));
extern void test_avx (void)
__attribute__((__target__("avx")));
extern void test_avx2 (void)
__attribute__((__target__("avx2")));
extern void test_avx512f (void)
__attribute__((__target__("avx512f")));
+extern void test_avx512vl(void)
__attribute__((__target__("avx512vl")));
+extern void test_avx512bw(void)
__attribute__((__target__("avx512bw")));
+extern void test_avx512dq(void)
__attribute__((__target__("avx512dq")));
+extern void test_avx512er(void)
__attribute__((__target__("avx512er")));
+extern void test_avx512pf(void)
__attribute__((__target__("avx512pf")));
+extern void test_avx512cd(void)
__attribute__((__target__("avx512cd")));
extern void test_bmi (void)
__attribute__((__target__("bmi")));
extern void test_bmi2 (void)
__attribute__((__target__("bmi2")));
@@ -50,6 +56,12 @@ extern void test_no_tbm (void)
__attribute__((__target__("no-tbm")));
extern void test_no_avx (void)
__attribute__((__target__("no-avx")));
extern void test_no_avx2 (void)
__attribute__((__target__("no-avx2")));
extern void test_no_avx512f (void)
__attribute__((__target__("no-avx512f")));
+extern void test_no_avx512vl(void)
__attribute__((__target__("no-avx512vl")));
+extern void test_no_avx512bw(void)
__attribute__((__target__("no-avx512bw")));
+extern void test_no_avx512dq(void)
__attribute__((__target__("no-avx512dq")));
+extern void test_no_avx512er(void)
__attribute__((__target__("no-avx512er")));
+extern void test_bo_avx512pf(void)
__attribute__((__target__("no-avx512pf")));
+extern void test_no_avx512cd(void)
__attribute__((__target__("no-avx512cd")));
extern void test_no_bmi (void)
__attribute__((__target__("no-bmi")));
extern void test_no_bmi2 (void)
__attribute__((__target__("no-bmi2")));
@@ -77,6 +89,7 @@ extern void test_arch_corei7 (void)
__attribute__((__target__("arch=corei7")));
extern void test_arch_corei7_avx (void)
__attribute__((__target__("arch=corei7-avx")));
extern void test_arch_core_avx2 (void)
__attribute__((__target__("arch=core-avx2")));
extern void test_arch_knl (void)
__attribute__((__target__("arch=knl")));
+extern void test_arch_skylake_avx512 (void)
__attribute__((__target__("arch=skylake-avx512")));
extern void test_arch_geode (void)
__attribute__((__target__("arch=geode")));
extern void test_arch_k6 (void)
__attribute__((__target__("arch=k6")));
extern void test_arch_k6_2 (void)
__attribute__((__target__("arch=k6-2")));
diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index eaf2f10..3abf04f 100644
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -36,7 +36,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If
not, see
int __cpu_indicator_init (void)
__attribute__ ((constructor CONSTRUCTOR_PRIORITY));
-/* Processor Vendor and Models. */
+/* Processor Vendor and Models. */
enum processor_vendor
{
@@ -46,7 +46,7 @@ enum processor_vendor
VENDOR_MAX
};
-/* Any new types or subtypes have to be inserted at the end. */
+/* Any new types or subtypes have to be inserted at the end. */
enum processor_types
{
@@ -76,10 +76,11 @@ enum processor_subtypes
INTEL_COREI7_IVYBRIDGE,
INTEL_COREI7_HASWELL,
INTEL_COREI7_BROADWELL,
+ INTEL_COREI7_SKYLAKE_AVX512,
CPU_SUBTYPE_MAX
};
-/* ISA Features supported. */
+/* ISA Features supported. New features have to be inserted at the end. */
enum processor_features
{
@@ -100,7 +101,15 @@ enum processor_features
FEATURE_FMA,
FEATURE_AVX512F,
FEATURE_BMI,
- FEATURE_BMI2
+ FEATURE_BMI2,
+ FEATURE_AES,
+ FEATURE_PCLMUL,
+ FEATURE_AVX512VL,
+ FEATURE_AVX512BW,
+ FEATURE_AVX512DQ,
+ FEATURE_AVX512CD,
+ FEATURE_AVX512ER,
+ FEATURE_AVX512PF
};
struct __processor_model
@@ -171,7 +180,7 @@ get_amd_cpu (unsigned int family, unsigned int model)
static void
get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
{
- /* Parse family and model only if brand ID is 0. */
+ /* Parse family and model only if brand ID is 0. */
if (brand_id == 0)
{
switch (family)
@@ -237,6 +246,11 @@ get_intel_cpu (unsigned int family, unsigned int model,
unsigned int brand_id)
__cpu_model.__cpu_type = INTEL_COREI7;
__cpu_model.__cpu_subtype = INTEL_COREI7_BROADWELL;
break;
+ case 0x55:
+ /* Skylake with AVX-512 support. */
+ __cpu_model.__cpu_type = INTEL_COREI7;
+ __cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE_AVX512;
+ break;
case 0x17:
case 0x1d:
/* Penryn. */
@@ -273,6 +287,10 @@ get_available_features (unsigned int ecx, unsigned int edx,
features |= (1 << FEATURE_SSE2);
if (ecx & bit_POPCNT)
features |= (1 << FEATURE_POPCNT);
+ if (ecx & bit_AES)
+ features |= (1 << FEATURE_AES);
+ if (ecx & bit_PCLMUL)
+ features |= (1 << FEATURE_PCLMUL);
if (ecx & bit_SSE3)
features |= (1 << FEATURE_SSE3);
if (ecx & bit_SSSE3)
@@ -299,6 +317,18 @@ get_available_features (unsigned int ecx, unsigned int edx,
features |= (1 << FEATURE_BMI2);
if (ebx & bit_AVX512F)
features |= (1 << FEATURE_AVX512F);
+ if (ebx & bit_AVX512VL)
+ features |= (1 << FEATURE_AVX512VL);
+ if (ebx & bit_AVX512BW)
+ features |= (1 << FEATURE_AVX512BW);
+ if (ebx & bit_AVX512DQ)
+ features |= (1 << FEATURE_AVX512DQ);
+ if (ebx & bit_AVX512CD)
+ features |= (1 << FEATURE_AVX512CD);
+ if (ebx & bit_AVX512PF)
+ features |= (1 << FEATURE_AVX512PF);
+ if (ebx & bit_AVX512ER)
+ features |= (1 << FEATURE_AVX512ER);
}
unsigned int ext_level;
