On Mon, 2015-10-05 at 13:12 -0400, Michael Meissner wrote:
> I have attached a better version of the patch.
I'll note that I have not committed the earlier patch and will hold
off while we sort out what is best here.
> This gives the constraints:
>
> #1: op0 = m, op1 = d, op2 = d
> #2: op0 = Y, op1 = r, op2 = r
> #3: op0 = d, op1 = ws, op2 = j
> #4: op0 = d, op1 = md, op2 = m
> #5: op0 = &d, op1 = m, op2 = md
>
> I.e.
>
> #1: Store result, input in FPR register, 0.0 in FPR register
> #2: Store result, input in GPR register, 0.0 in GPR register
> #3: Result in FPR reg, input in VSX reg, 0.0 direct (VSX only)
> #4: Result in FPR reg, input in FPR/memory, 0.0 in memory
> #5: Result in FPR reg, input in FPR/memory, 0.0 in FPR/memory (no overlap)
As we discussed on IRC, this alt #3 now does not accept memory as an
input operand and that is the only alternative that allows us to
generate a xxlxor to create a zero fp value. Either we can change #3's
opt1 from "ws" to "mws" or just create another alternative. I'll let
you decide what works best.
Since this test is testing whether we ICE when -mlra -mvsx is enabled,
how about if we verify we're also getting the xxlxor too, with the
addition of:
/* { dg-final { scan-assembler-times "xxlxor" 1 } } */
to the test case?
Peter
