Hi all,
In this PR we ICE when compiling with -mtune=xscale. The ICE is a
segfault in xscale_sched_adjust_cost.
The root cause is that xscale_sched_adjust_cost uses the value of the
'shift' insn attribute to index
the recog operands. In GCC 5 the form and number of operands in those
patterns were updated but the
shift value was not:
Author: rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu May 29 09:39:07 2014 +0000
* arm/iterators.md (shiftable_ops): New code iterator.
(t2_binop0, arith_shift_insn): New code attributes.
* arm/predicates.md (shift_nomul_operator): New predicate.
* arm/arm.md (insn_enabled): Delete.
(enabled): Remove insn_enabled test.
(*arith_shiftsi): Delete. Replace with ...
(*<arith_shift_insn>_multsi): ... new pattern.
(*<arith_shift_insn>_shiftsi): ... new pattern.
* config/arm/arm.c (arm_print_operand): Handle operand format 'b'.
This led to an out-of-bounds array access. Only xscale_sched_adjust_cost
uses the shift
attribute, so the segfault only happens for xscale tuning. In the future
we might want
to use a more general pattern-matching approach to find the shifted
operand in an rtx...
In any case, this patch fixes the value of 'shift' for the offending
pattern and also
updates 'shift' for the *<arith_shift_insn>_shiftsi pattern to point to
the correct
operand that is being shifted.
Tested arm-none-eabi and bootstrapped with -mtune=xscale in BOOT_CFLAGS.
Ok for trunk?
Thanks,
Kyrill
2014-01-12 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
PR target/64460
* config/arm/arm.md (*<arith_shift_insn>_multsi): Set 'shift' attr
to 2.
(*<arith_shift_insn>_shiftsi): Set 'shift' attr to 3.
2014-01-12 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
PR target/64460
* gcc.target/arm/pr64460_1.c: New test.
