2011/3/21 Andrey Belevantsev <a...@ispras.ru>: > Hello, > > As noted in the PR audit trail, the scheduler crashes for this bug because > we see an SSE insn without proper reservation. Uros has pointed several > such insns to me. The following patch adding athlon_decode attributes is > bootstrapped and tested on x86_64. > > Uros, you have preapproved the patch idea, but does it still look ok to you? > I have mostly copied reservations from bdver1 variants. > > Richi, Jakub, do you want this in 4.6.1? 4.6.0? > > Andrey > > > 2011-03-21 Andrey Belevantsev <a...@ispras.ru> > > PR rtl-optimization/48143 > * config/i386/sse.md (*sse2_cvtpd2dq): Add athlon_decode attribute. > (*sse2_cvttpd2dq, sse2_cvtss2sd, *sse2_cvtpd2ps, > sse2_cvtps2pd): Likewise.
Can you please cross-check these added attribute with the values in Chapter C.7 (Table 18) and C.8 (Table 19) in [1] ? Otherwise, the patch is OK. [1] http://support.amd.com/us/Processor_TechDocs/25112.PDF Thanks, Uros.
