Hello,
As noted in the PR audit trail, the scheduler crashes for this bug because
we see an SSE insn without proper reservation. Uros has pointed several
such insns to me. The following patch adding athlon_decode attributes is
bootstrapped and tested on x86_64.
Uros, you have preapproved the patch idea, but does it still look ok to
you? I have mostly copied reservations from bdver1 variants.
Richi, Jakub, do you want this in 4.6.1? 4.6.0?
Andrey
2011-03-21 Andrey Belevantsev <a...@ispras.ru>
PR rtl-optimization/48143
* config/i386/sse.md (*sse2_cvtpd2dq): Add athlon_decode attribute.
(*sse2_cvttpd2dq, sse2_cvtss2sd, *sse2_cvtpd2ps,
sse2_cvtps2pd): Likewise.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 6200419..a50db12 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2715,6 +2715,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")
+ (set_attr "athlon_decode" "double")
(set_attr "bdver1_decode" "double")])
(define_insn "avx_cvttpd2dq256"
@@ -2746,6 +2747,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")
+ (set_attr "athlon_decode" "double")
(set_attr "bdver1_decode" "double")])
(define_insn "*avx_cvtsd2ss"
@@ -2806,6 +2808,7 @@
"cvtss2sd\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt")
(set_attr "amdfam10_decode" "vector,double")
+ (set_attr "athlon_decode" "direct,direct")
(set_attr "bdver1_decode" "direct,direct")
(set_attr "mode" "DF")])
@@ -2842,6 +2845,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")
(set_attr "amdfam10_decode" "double")
+ (set_attr "athlon_decode" "double")
(set_attr "bdver1_decode" "double")])
(define_insn "avx_cvtps2pd256"
@@ -2879,6 +2883,7 @@
(set_attr "mode" "V2DF")
(set_attr "prefix_data16" "0")
(set_attr "amdfam10_decode" "direct")
+ (set_attr "athlon_decode" "double")
(set_attr "bdver1_decode" "double")])
(define_expand "vec_unpacks_hi_v4sf"
