https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127498
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jakub Jelinek <[email protected]>: https://gcc.gnu.org/g:fcecd85661f9947d09dd752124279fc537021106 commit r17-4508-gfcecd85661f9947d09dd752124279fc537021106 Author: Jakub Jelinek <[email protected]> Date: Mon Sep 21 09:13:34 2026 +0200 i386: Only support GFNI V32QImode rotates with AVX2, not just AVX [PR127498] The following testcase ICEs, because the middle-end doesn't like a target to announce rot{l,r}v32qi3 optab availability only with const_int_operand rotate with non-working fallback. If the rotate optab fails because of unsatisfiable predicates, the middle-end will try to expand the rotate as bitwise or of 2 shifts, but the problem with TARGET_GFNI && TARGET_AVX && !TARGET_AVX2 is that the V32QImode shifts aren't supported either, one needs AVX2 for that. I believe there are no CPUs with GFNI and AVX but without AVX2, I think there are just CPUs with both GFNI and AVX/AVX2 or with GFNI and no AVX, so the following patch just disables the pattern for the TARGET_GFNI && TARGET_AVX combination and just requires TARGET_GFNI && TARGET_AVX2 instead. It is true that rotate can be expanded with constant rotate count even for V32QImode, but at the expense of ICEing for non-constant rotate count. The alternative would be to extend the pattern to provide a fallback for TARGET_GFNI && TARGET_AVX && !TARGET_AVX2 when the last operand is not const_int_operand, it can be handled as 4 V16QImode shifts, combining stuff together, ... 2026-09-21 Jakub Jelinek <[email protected]> PR target/127498 * config/i386/sse.md (<insn><mode>3 any_rotate:VI1_AVX512_3264): Add TARGET_AVX2 to condition. * gcc.target/i386/gfni-pr127498.c: New test. * gcc.target/i386/shift-gf2p8affine-5.c: Use -mavx2 in dg-options instead of -mavx. Expect 46 insns instead of 31. Reviewed-by: Hongtao Liu <[email protected]>
