https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127498
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |ak at gcc dot gnu.org
--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I think the problem is that
(define_expand "<insn><mode>3"
[(set (match_operand:VI1_AVX512_3264 0 "register_operand")
(any_rotate:VI1_AVX512_3264
(match_operand:VI1_AVX512_3264 1 "register_operand")
(match_operand:SI 2 "const_int_operand")))]
"TARGET_GFNI"
{
rtx matrix = ix86_vgf2p8affine_shift_matrix (operands[0], operands[2],
<CODE>);
emit_insn (gen_vgf2p8affineqb_<mode> (operands[0], operands[1], matrix,
const0_rtx));
DONE;
})
for V32QImode only handles constant last operand, but the generic code doesn't
differentiate between constant and non-constant last operand when looking at
optab.
And with AVX without AVX2, fallback is not possible, because V32QImode left and
right shift are not supported, one needs veclower to split it into 2 V16QImode
operations.
So, one possible fix is
--- a/gcc/config/i386/sse.md 2026-09-15 12:01:51.693090054 +0200
+++ b/gcc/config/i386/sse.md 2026-09-19 09:40:29.237554809 +0200
@@ -388,7 +388,7 @@
[V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")])
(define_mode_iterator VI1_AVX512_3264
- [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX")])
+ [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX2")])
;; All vector modes
(define_mode_iterator V
so stop supporting the V32QImode rotates for TARGET_GFNI && TARGET_AVX &&
!TARGET_AVX2.
>From what I can read, the only CPUs with GFNI without AVX2 are Tremont and
those don't have AVX either.
The other option (hard) would be to change the pattern not to support just
const_int_operand but nonmemory_operand and somehow manually expand it in the
TARGET_GFNI && TARGET_AVX && !TARGET_AVX2 for V32QImode.
