https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127264
--- Comment #4 from Haochen Jiang <haochen.jiang at intel dot com> ---
(In reply to Jakub Jelinek from comment #2)
> Anyway, the RTL patterns look just weird:
> (define_insn "tilezero"
> [(set (reg:V32SI TMM_REGNUM)
> (unspec_volatile:V32SI
> [(match_operand:QI 0 "const_0_to_7_operand")]
> UNSPECV_TILEZERO))]
> "TARGET_ACEV1"
> "tilezero\t{%%tmm%c0|tmm%c0}"
> [(set_attr "prefix" "vex")])
> That is as if there is just one TMM_REGNUM register fully set by the
> instruction, but it seems that there are 8 of the tmm registers (and each of
> those is 8192 bit, so that would be V256SI)?
tilezero should only zero the corresponding tmm register, not all tmm
registers. That operand is for the reg number want to be zeroed.
