[Bug target/127264] [17 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in ix86_expand_ace_builtin, at config/i386/i386-expand.cc:14776 with -macev1

[jakub at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127264

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Anyway, the RTL patterns look just weird:
(define_insn "tilezero"
  [(set (reg:V32SI TMM_REGNUM)
        (unspec_volatile:V32SI
          [(match_operand:QI 0 "const_0_to_7_operand")]
          UNSPECV_TILEZERO))]
  "TARGET_ACEV1"
  "tilezero\t{%%tmm%c0|tmm%c0}"
  [(set_attr "prefix" "vex")])
That is as if there is just one TMM_REGNUM register fully set by the
instruction, but it seems that there are 8 of the tmm registers (and each of
those is 8192 bit, so that would be V256SI)?