[Bug rtl-optimization/126165] INSN_SCHEDULING should generate reg->reg move instead of load

[hjl.tools at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126165

--- Comment #1 from H.J. Lu <hjl.tools at gmail dot com> ---
Created attachment 65000
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=65000&action=edit
A patch to extend postreload

reload_cse_simplify_set calls cselib_lookup to lookup the rtl expression
in cselib_hash_table.  In the case of

(insn 3 11 4 2 (set (mem/c:DI (plus:DI (reg/f:DI 7 sp)
                (const_int 40 [0x28])) [0  S8 A8])
        (reg:DI 4 si)) "x.c":7:1 99 {*movdi_internal}
     (nil))
...
(insn 105 104 107 2 (set (reg:SI 4 si)
        (mem:SI (plus:DI (reg/f:DI 7 sp)
                (const_int 40 [0x28])) [0 MEM[(int * {ref-all})addr.2_30]+0 S4
A32])) "x.c":15:3 100 {*movsi_internal}
     (nil))

it missed that

(mem:SI (plus:DI (reg/f:DI 7 sp) (const_int 40 [0x28])))

was covered by

(mem:DI (plus:DI (reg/f:DI 7 sp) (const_int 40 [0x28])))

Update reload_cse_simplify_set to lookup the wider memory if the number
of bytes between the start of the narrower mode and the start of the
wider mode in memory and register is 0 so that load from memory in the
narrower mode is the same as move from register in the narrower mode.  If
cselib_lookup returns a wider result which can be used in the narrower
mode and cost is lower than or equal to load from memory, move from the
wider result in the narrower mode.  We replace

(insn 105 104 107 2 (set (reg:SI 4 si)
        (mem:SI (plus:DI (reg/f:DI 7 sp)
                (const_int 40 [0x28])) [0 MEM[(int * {ref-all})addr.2_30]+0 S4
A32])) "x.c":15:3 100 {*movsi_internal}
     (nil))

with

(insn 105 104 107 2 (set (reg:SI 4 si)
        (reg:SI 4 si)) "x.c":15:3 -1
     (nil))