[Bug target/118075] [15 Regression] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118075

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:46194b912780452e80c1ef9867cbcff1050231a2

commit r15-6362-g46194b912780452e80c1ef9867cbcff1050231a2
Author: Pan Li <pan2...@intel.com>
Date:   Thu Dec 19 08:58:20 2024 +0800

    RISC-V: Make vector strided store alias all other memories

    Almost the same as the RVV strided load, the vector strided store
    doesn't involve the (mem:BLK (scratch)) to alias all other memories.
    It will make the alias analysis only consider the base address of
    strided store.

            PR target/118075

    gcc/ChangeLog:

            * config/riscv/vector.md: Add the (mem:BLK (scratch)) as the
            lhs of strided store define insn.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr118075-run-1.c: New test.

    Signed-off-by: Pan Li <pan2...@intel.com>