[Bug target/118075] [15 Regression] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610

[pan2.li at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118075

--- Comment #2 from Li Pan <pan2.li at intel dot com> ---
Ack and reproduced.
Take a rough look it should be the strided store for memory alias because
disable the sch can fix it.

I will take care of it.