[Bug tree-optimization/116583] vectorizable_slp_permutation cannot handle even/odd extract from VLA vector

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116583

--- Comment #11 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Richard Sandiford <rsand...@gcc.gnu.org>:

https://gcc.gnu.org/g:1048ebbbdc98a5928a974356d7f4244603b6bd32

commit r15-4110-g1048ebbbdc98a5928a974356d7f4244603b6bd32
Author: Richard Sandiford <richard.sandif...@arm.com>
Date:   Mon Oct 7 13:03:02 2024 +0100

    aarch64: Handle SVE modes in aarch64_evpc_reencode [PR116583]

    For Advanced SIMD modes, aarch64_evpc_reencode tests whether
    a permute in a narrow element mode can be done more cheaply
    in a wider mode.  For example, { 0, 1, 8, 9, 4, 5, 12, 13 }
    on V8HI is a natural TRN1 on V4SI ({ 0, 4, 2, 6 }).

    This patch extends the code to handle SVE data and predicate
    modes as well.  This is a prerequisite to getting good results
    for PR116583.

    gcc/
            PR target/116583
            * config/aarch64/aarch64.cc (aarch64_coalesce_units): New function,
            extending the Advanced SIMD handling from...
            (aarch64_evpc_reencode): ...here to SVE data and predicate modes.

    gcc/testsuite/
            PR target/116583
            * gcc.target/aarch64/sve/permute_1.c: New test.
            * gcc.target/aarch64/sve/permute_2.c: Likewise.
            * gcc.target/aarch64/sve/permute_3.c: Likewise.
            * gcc.target/aarch64/sve/permute_4.c: Likewise.