[Bug middle-end/111548] RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass)

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111548

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:9d5f20fc4a6b3254d2d379309193da4be2747987

commit r14-4248-g9d5f20fc4a6b3254d2d379309193da4be2747987
Author: Juzhe-Zhong <juzhe.zh...@rivai.ai>
Date:   Sun Sep 24 11:17:01 2023 +0800

    RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548]

    This patch fixes that AVL/VL reg incorrect fetch in VSETVL PASS.

    C/C++ regression passed.

    But gfortran didn't run yet. I am still finding a way to run it.

    Will commit it when I pass the fortran regression.

            PR target/111548

    gcc/ChangeLog:

            * config/riscv/riscv-vsetvl.cc (earliest_pred_can_be_fused_p):
Bugfix

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr111548.c: New test.