https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99195
--- Comment #16 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Kyrylo Tkachov <ktkac...@gcc.gnu.org>: https://gcc.gnu.org/g:b30ab0dcf9db2ac6d81fb3743add1fbfa0d18f6e commit r14-1167-gb30ab0dcf9db2ac6d81fb3743add1fbfa0d18f6e Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com> Date: Wed May 24 14:52:34 2023 +0100 aarch64: PR target/99195 Annotate vector shift patterns for vec-concat-zero Continuing the series of straightforward annotations, this one handles the normal (not widening or narrowing) vector shifts. Tests included. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_simd_lshr<mode>): Rename to... (aarch64_simd_lshr<mode><vczle><vczbe>): ... This. (aarch64_simd_ashr<mode>): Rename to... (aarch64_simd_ashr<mode><vczle><vczbe>): ... This. (aarch64_simd_imm_shl<mode>): Rename to... (aarch64_simd_imm_shl<mode><vczle><vczbe>): ... This. (aarch64_simd_reg_sshl<mode>): Rename to... (aarch64_simd_reg_sshl<mode><vczle><vczbe>): ... This. (aarch64_simd_reg_shl<mode>_unsigned): Rename to... (aarch64_simd_reg_shl<mode>_unsigned<vczle><vczbe>): ... This. (aarch64_simd_reg_shl<mode>_signed): Rename to... (aarch64_simd_reg_shl<mode>_signed<vczle><vczbe>): ... This. (vec_shr_<mode>): Rename to... (vec_shr_<mode><vczle><vczbe>): ... This. (aarch64_<sur>shl<mode>): Rename to... (aarch64_<sur>shl<mode><vczle><vczbe>): ... This. (aarch64_<sur>q<r>shl<mode>): Rename to... (aarch64_<sur>q<r>shl<mode><vczle><vczbe>): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add testing for shifts. * gcc.target/aarch64/simd/pr99195_6.c: Likewise. * gcc.target/aarch64/simd/pr99195_8.c: New test.
